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Merge tag 'riscv-dt-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.11 T-Head: Last change from me before this starts going via Drew's tree is the addition of the SBI PMU events node for the th1520. StarFive: A dts for the Pin64 Star64, another board with a jh7110 SoC. This board is almost identical to the existing Milk-v Mars and VisionFive 2 boards that are already support - just with a different PHY configuration and only one of the two PCIe ports exposed. Additionally, the Mars and VisionFive 2 get their PCie configuration added. Microchip: A dts for the BeagleV Fire. PCIe is disabled on it for now, as some binding and driver changes are required. Signed-off-by: Conor Dooley <[email protected]> * tag 'riscv-dt-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: add PCIe dts configuration for JH7110 riscv: dts: microchip: add an initial devicetree for the BeagleV Fire dt-bindings: riscv: microchip: document beaglev-fire riscv: dts: starfive: Update flash partition layout riscv: dts: thead: th1520: Add PMU event node riscv: dts: starfive: add Star64 board devicetree dt-bindings: riscv: starfive: add Star64 board compatible dt-bindings: riscv: Add T-HEAD C908 compatible Link: https://lore.kernel.org/r/20240707-nuttiness-lustfully-4aaf03c991b2@spud Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/riscv/cpus.yaml

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@@ -47,6 +47,7 @@ properties:
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- sifive,u74
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- sifive,u74-mc
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- thead,c906
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- thead,c908
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- thead,c910
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- thead,c920
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- const: riscv

‎Documentation/devicetree/bindings/riscv/microchip.yaml

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- enum:
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- aldec,tysom-m-mpfs250t-rev2
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- aries,m100pfsevp
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- beagle,beaglev-fire
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- microchip,mpfs-sev-kit
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- sundance,polarberry
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- const: microchip,mpfs

‎Documentation/devicetree/bindings/riscv/starfive.yaml

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- items:
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- enum:
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- milkv,mars
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- pine64,star64
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- starfive,visionfive-2-v1.2a
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- starfive,visionfive-2-v1.3b
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- const: starfive,jh7110

‎arch/riscv/boot/dts/microchip/Makefile

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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb

‎arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/ {
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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fabric-bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
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<0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
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<0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
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<0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
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<0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
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cape_gpios_p8: gpio@41100000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x41100000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
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"P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
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"P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
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"P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
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};
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cape_gpios_p9: gpio@41200000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x41200000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <20>;
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gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
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"P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
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"P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
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"P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
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"P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
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};
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hsi_gpios: gpio@44000000 {
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compatible = "microchip,coregpio-rtl-v3";
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reg = <0x0 0x44000000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <20>;
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gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
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"B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
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"B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
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"XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
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"XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
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"XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
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"XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
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};
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};
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refclk_ccc: cccrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_nw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};

‎arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "mpfs.dtsi"
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#include "mpfs-beaglev-fire-fabric.dtsi"
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/* Clock frequency (in Hz) of MTIMER */
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#define MTIMER_FREQ 1000000
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "BeagleBoard BeagleV-Fire";
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compatible = "beagle,beaglev-fire", "microchip,mpfs";
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aliases {
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serial0 = &mmuart0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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serial3 = &mmuart3;
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serial4 = &mmuart4;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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timebase-frequency = <MTIMER_FREQ>;
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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status = "okay";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hss: hss-buffer@103fc00000 {
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compatible = "shared-dma-pool";
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reg = <0x10 0x3fc00000 0x0 0x400000>;
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no-map;
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};
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};
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imx219_clk: camera-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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imx219_vana: fixedregulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "imx219_vana";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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imx219_vdig: fixedregulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "imx219_vdig";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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imx219_vddl: fixedregulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "imx219_vddl";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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};
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&gpio2 {
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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ngpios=<32>;
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gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
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"P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
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"P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
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"P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
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"P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20",
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"P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26",
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"P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1",
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"M2_W_DISABLE2", "VIO_ENABLE", "SD_DET";
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status = "okay";
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vio-enable-hog {
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gpio-hog;
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gpios = <30 30>;
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output-high;
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line-name = "VIO_ENABLE";
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};
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sd-det-hog {
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gpio-hog;
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gpios = <31 31>;
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input;
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line-name = "SD_DET";
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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eeprom: eeprom@50 {
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compatible = "atmel,24c32";
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reg = <0x50>;
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};
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imx219: sensor@10 {
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compatible = "sony,imx219";
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reg = <0x10>;
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clocks = <&imx219_clk>;
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VANA-supply = <&imx219_vana>; /* 2.8v */
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VDIG-supply = <&imx219_vdig>; /* 1.8v */
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VDDL-supply = <&imx219_vddl>; /* 1.2v */
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port {
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imx219_0: endpoint {
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data-lanes = <1 2>;
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clock-noncontinuous;
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link-frequencies = /bits/ 64 <456000000>;
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};
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};
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};
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};
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&mac0 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&mbox {
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status = "okay";
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};
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&mmc {
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&mmuart0 {
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status = "okay";
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};
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&mmuart1 {
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status = "okay";
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&refclk_ccc {
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clock-frequency = <50000000>;
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};
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&rtc {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&spi1 {
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status = "okay";
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};
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&syscontroller {
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microchip,bitstream-flash = <&sys_ctrl_flash>;
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status = "okay";
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};
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&syscontroller_qspi {
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status = "okay";
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sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
211+
compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <20000000>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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};
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};
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&usb {
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status = "okay";
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dr_mode = "otg";
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};

‎arch/riscv/boot/dts/starfive/Makefile

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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
1314
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb

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