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Merge tag 'v5.7-next-dts64.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
mt8183: - add PMIC mt6358 - add MMC node mt2712: - enable APDMA for the uart node - add ethernet gmac node mmsys: - change node name to syscon as mmsys no longer represents only clocks but also the DRM subsystem * tag 'v5.7-next-dts64.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm: dts: mt2712: add uart APDMA to device tree arm64: dts: mt8183: add mmc node arm64: dts: mt2712: add ethernet device node arm64: dts: mt6358: add PMIC MT6358 related nodes arm64: dts: mt6797: Fix mmsys node name arm64: dts: mt8173: Fix mmsys node name Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎arch/arm64/boot/dts/mediatek/mt2712-evb.dts

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,81 @@
105105
proc-supply = <&cpus_fixed_vproc1>;
106106
};
107107

108+
&eth {
109+
phy-mode ="rgmii-rxid";
110+
phy-handle = <&ethernet_phy0>;
111+
mediatek,tx-delay-ps = <1530>;
112+
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
113+
pinctrl-names = "default", "sleep";
114+
pinctrl-0 = <&eth_default>;
115+
pinctrl-1 = <&eth_sleep>;
116+
status = "okay";
117+
118+
mdio {
119+
compatible = "snps,dwmac-mdio";
120+
#address-cells = <1>;
121+
#size-cells = <0>;
122+
ethernet_phy0: ethernet-phy@5 {
123+
compatible = "ethernet-phy-id0243.0d90";
124+
reg = <0x5>;
125+
};
126+
};
127+
};
128+
108129
&pio {
130+
eth_default: eth_default {
131+
tx_pins {
132+
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
133+
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
134+
<MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1>,
135+
<MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,
136+
<MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,
137+
<MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;
138+
drive-strength = <MTK_DRIVE_8mA>;
139+
};
140+
rx_pins {
141+
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,
142+
<MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2>,
143+
<MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1>,
144+
<MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0>,
145+
<MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV>,
146+
<MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC>;
147+
input-enable;
148+
};
149+
mdio_pins {
150+
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,
151+
<MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;
152+
drive-strength = <MTK_DRIVE_8mA>;
153+
input-enable;
154+
};
155+
};
156+
157+
eth_sleep: eth_sleep {
158+
tx_pins {
159+
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
160+
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
161+
<MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73>,
162+
<MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74>,
163+
<MT2712_PIN_75_GBE_TXC__FUNC_GPIO75>,
164+
<MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76>;
165+
};
166+
rx_pins {
167+
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78>,
168+
<MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79>,
169+
<MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80>,
170+
<MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81>,
171+
<MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82>,
172+
<MT2712_PIN_84_GBE_RXC__FUNC_GPIO84>;
173+
input-disable;
174+
};
175+
mdio_pins {
176+
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GPIO85>,
177+
<MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86>;
178+
input-disable;
179+
bias-disable;
180+
};
181+
};
182+
109183
usb0_id_pins_float: usb0_iddig {
110184
pins_iddig {
111185
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;

‎arch/arm64/boot/dts/mediatek/mt2712e.dtsi

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,9 @@
300300
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
301301
clocks = <&baud_clk>, <&sys_clk>;
302302
clock-names = "baud", "bus";
303+
dmas = <&apdma 10
304+
&apdma 11>;
305+
dma-names = "tx", "rx";
303306
status = "disabled";
304307
};
305308

@@ -375,6 +378,39 @@
375378
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
376379
};
377380

381+
apdma: dma-controller@11000400 {
382+
compatible = "mediatek,mt2712-uart-dma",
383+
"mediatek,mt6577-uart-dma";
384+
reg = <0 0x11000400 0 0x80>,
385+
<0 0x11000480 0 0x80>,
386+
<0 0x11000500 0 0x80>,
387+
<0 0x11000580 0 0x80>,
388+
<0 0x11000600 0 0x80>,
389+
<0 0x11000680 0 0x80>,
390+
<0 0x11000700 0 0x80>,
391+
<0 0x11000780 0 0x80>,
392+
<0 0x11000800 0 0x80>,
393+
<0 0x11000880 0 0x80>,
394+
<0 0x11000900 0 0x80>,
395+
<0 0x11000980 0 0x80>;
396+
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
397+
<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
398+
<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
399+
<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
400+
<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
401+
<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
402+
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
403+
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
404+
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
405+
<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
406+
<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
407+
<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
408+
dma-requests = <12>;
409+
clocks = <&pericfg CLK_PERI_AP_DMA>;
410+
clock-names = "apdma";
411+
#dma-cells = <1>;
412+
};
413+
378414
auxadc: adc@11001000 {
379415
compatible = "mediatek,mt2712-auxadc";
380416
reg = <0 0x11001000 0 0x1000>;
@@ -391,6 +427,9 @@
391427
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
392428
clocks = <&baud_clk>, <&sys_clk>;
393429
clock-names = "baud", "bus";
430+
dmas = <&apdma 0
431+
&apdma 1>;
432+
dma-names = "tx", "rx";
394433
status = "disabled";
395434
};
396435

@@ -401,6 +440,9 @@
401440
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
402441
clocks = <&baud_clk>, <&sys_clk>;
403442
clock-names = "baud", "bus";
443+
dmas = <&apdma 2
444+
&apdma 3>;
445+
dma-names = "tx", "rx";
404446
status = "disabled";
405447
};
406448

@@ -411,6 +453,9 @@
411453
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
412454
clocks = <&baud_clk>, <&sys_clk>;
413455
clock-names = "baud", "bus";
456+
dmas = <&apdma 4
457+
&apdma 5>;
458+
dma-names = "tx", "rx";
414459
status = "disabled";
415460
};
416461

@@ -421,6 +466,9 @@
421466
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
422467
clocks = <&baud_clk>, <&sys_clk>;
423468
clock-names = "baud", "bus";
469+
dmas = <&apdma 6
470+
&apdma 7>;
471+
dma-names = "tx", "rx";
424472
status = "disabled";
425473
};
426474

@@ -635,6 +683,74 @@
635683
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
636684
clocks = <&baud_clk>, <&sys_clk>;
637685
clock-names = "baud", "bus";
686+
dmas = <&apdma 8
687+
&apdma 9>;
688+
dma-names = "tx", "rx";
689+
status = "disabled";
690+
};
691+
692+
stmmac_axi_setup: stmmac-axi-config {
693+
snps,wr_osr_lmt = <0x7>;
694+
snps,rd_osr_lmt = <0x7>;
695+
snps,blen = <0 0 0 0 16 8 4>;
696+
};
697+
698+
mtl_rx_setup: rx-queues-config {
699+
snps,rx-queues-to-use = <1>;
700+
snps,rx-sched-sp;
701+
queue0 {
702+
snps,dcb-algorithm;
703+
snps,map-to-dma-channel = <0x0>;
704+
snps,priority = <0x0>;
705+
};
706+
};
707+
708+
mtl_tx_setup: tx-queues-config {
709+
snps,tx-queues-to-use = <3>;
710+
snps,tx-sched-wrr;
711+
queue0 {
712+
snps,weight = <0x10>;
713+
snps,dcb-algorithm;
714+
snps,priority = <0x0>;
715+
};
716+
queue1 {
717+
snps,weight = <0x11>;
718+
snps,dcb-algorithm;
719+
snps,priority = <0x1>;
720+
};
721+
queue2 {
722+
snps,weight = <0x12>;
723+
snps,dcb-algorithm;
724+
snps,priority = <0x2>;
725+
};
726+
};
727+
728+
eth: ethernet@1101c000 {
729+
compatible = "mediatek,mt2712-gmac";
730+
reg = <0 0x1101c000 0 0x1300>;
731+
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
732+
interrupt-names = "macirq";
733+
mac-address = [00 55 7b b5 7d f7];
734+
clock-names = "axi",
735+
"apb",
736+
"mac_main",
737+
"ptp_ref";
738+
clocks = <&pericfg CLK_PERI_GMAC>,
739+
<&pericfg CLK_PERI_GMAC_PCLK>,
740+
<&topckgen CLK_TOP_ETHER_125M_SEL>,
741+
<&topckgen CLK_TOP_ETHER_50M_SEL>;
742+
assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
743+
<&topckgen CLK_TOP_ETHER_50M_SEL>;
744+
assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
745+
<&topckgen CLK_TOP_APLL1_D3>;
746+
power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
747+
mediatek,pericfg = <&pericfg>;
748+
snps,axi-config = <&stmmac_axi_setup>;
749+
snps,mtl-rx-config = <&mtl_rx_setup>;
750+
snps,mtl-tx-config = <&mtl_tx_setup>;
751+
snps,txpbl = <1>;
752+
snps,rxpbl = <1>;
753+
clk_csr = <0>;
638754
status = "disabled";
639755
};
640756

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