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Merge tag 'irq-core-2020-01-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "The interrupt departement provides: - A mechanism to shield isolated tasks from managed interrupts: The affinity of managed interrupts is completely controlled by the kernel and user space has no influence on them. The reason is that the automatically assigned affinity correlates to the multi-queue CPU handling of block devices. If the generated affinity mask spaws both housekeeping and isolated CPUs the interrupt could be routed to an isolated CPU which would then be disturbed by I/O submitted by a housekeeping CPU. The new mechamism ensures that as long as one housekeeping CPU is online in the assigned affinity mask the interrupt is routed to a housekeeping CPU. If there is no online housekeeping CPU in the affinity mask, then the interrupt is routed to an isolated CPU to keep the device queue intact, but unless the isolated CPU submits I/O by itself these interrupts are not raised. - A small addon to the device tree irqdomain core code to avoid duplication in irq chip drivers - Conversion of the SiFive PLIC to hierarchical domains - The usual pile of new irq chip drivers: SiFive GPIO, Aspeed SCI, NXP INTMUX, Meson A1 GPIO - The first cut of support for the new ARM GICv4.1 - The usual pile of fixes and improvements in core and driver code" * tag 'irq-core-2020-01-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (33 commits) genirq, sched/isolation: Isolate from handling managed interrupts irqchip/gic-v4.1: Allow direct invalidation of VLPIs irqchip/gic-v4.1: Suppress per-VLPI doorbell irqchip/gic-v4.1: Add VPE INVALL callback irqchip/gic-v4.1: Add VPE eviction callback irqchip/gic-v4.1: Add VPE residency callback irqchip/gic-v4.1: Add mask/unmask doorbell callbacks irqchip/gic-v4.1: Plumb skeletal VPE irqchip irqchip/gic-v4.1: Implement the v4.1 flavour of VMOVP irqchip/gic-v4.1: Don't use the VPE proxy if RVPEID is set irqchip/gic-v4.1: Implement the v4.1 flavour of VMAPP irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation irqchip/gic-v3: Add GICv4.1 VPEID size discovery irqchip/gic-v3: Detect GICv4.1 supporting RVPEID irqchip/gic-v3-its: Fix get_vlpi_map() breakage with doorbells irqdomain: Fix a memory leak in irq_domain_push_irq() irqchip: Add NXP INTMUX interrupt multiplexer support dt-bindings: interrupt-controller: Add binding for NXP INTMUX interrupt multiplexer irqchip: Define EXYNOS_IRQ_COMBINER irqchip/meson-gpio: Add support for meson a1 SoCs ...
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‎Documentation/admin-guide/kernel-parameters.txt

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@@ -1934,9 +1934,31 @@
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<cpu number> begins at 0 and the maximum value is
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"number of CPUs in system - 1".
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The format of <cpu-list> is described above.
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managed_irq
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Isolate from being targeted by managed interrupts
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which have an interrupt mask containing isolated
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CPUs. The affinity of managed interrupts is
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handled by the kernel and cannot be changed via
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the /proc/irq/* interfaces.
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This isolation is best effort and only effective
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if the automatically assigned interrupt mask of a
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device queue contains isolated and housekeeping
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CPUs. If housekeeping CPUs are online then such
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interrupts are directed to the housekeeping CPU
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so that IO submitted on the housekeeping CPU
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cannot disturb the isolated CPU.
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If a queue's affinity mask contains only isolated
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CPUs then this parameter has no effect on the
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interrupt routing decision, though interrupts are
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only delivered when tasks running on those
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isolated CPUs submit IO. IO submitted on
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housekeeping CPUs has no influence on those
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queues.
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The format of <cpu-list> is described above.
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iucv= [HW,NET]
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‎Documentation/devicetree/bindings/gpio/sifive,gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive GPIO controller
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maintainers:
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- Yash Shah <[email protected]>
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- Paul Walmsley <[email protected]>
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properties:
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compatible:
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items:
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- const: sifive,fu540-c000-gpio
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- const: sifive,gpio0
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reg:
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maxItems: 1
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interrupts:
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description:
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interrupt mapping one per GPIO. Maximum 16 GPIOs.
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minItems: 1
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maxItems: 16
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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clocks:
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maxItems: 1
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"#gpio-cells":
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const: 2
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gpio-controller: true
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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- clocks
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- "#gpio-cells"
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- gpio-controller
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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gpio@10060000 {
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compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
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interrupt-parent = <&plic>;
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interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
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reg = <0x0 0x10060000 0x0 0x1000>;
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clocks = <&tlclk PRCI_CLK_TLCLK>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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...

‎Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

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"amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
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"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
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"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
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"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : Specifies the number of cells needed to encode an

‎Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt

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Aspeed AST25XX and AST26XX SCU Interrupt Controller
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Required Properties:
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- #interrupt-cells : must be 1
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- compatible : must be "aspeed,ast2500-scu-ic",
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"aspeed,ast2600-scu-ic0" or
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"aspeed,ast2600-scu-ic1"
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- interrupts : interrupt from the parent controller
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- interrupt-controller : indicates that the controller receives and
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fires new interrupts for child busses
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Example:
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syscon@1e6e2000 {
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ranges = <0 0x1e6e2000 0x1a8>;
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scu_ic: interrupt-controller@18 {
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#interrupt-cells = <1>;
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compatible = "aspeed,ast2500-scu-ic";
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interrupts = <21>;
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interrupt-controller;
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};
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};

‎Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale INTMUX interrupt multiplexer
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maintainers:
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- Joakim Zhang <[email protected]>
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properties:
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compatible:
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const: fsl,imx-intmux
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 8
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description: |
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Should contain the parent interrupt lines (up to 8) used to multiplex
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the input interrupts.
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description: |
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The 1st cell is hw interrupt number, the 2nd cell is channel index.
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clocks:
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description: ipg clock.
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clock-names:
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const: ipg
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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interrupt-controller@37400000 {
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compatible = "fsl,imx-intmux";
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reg = <0x37400000 0x1000>;
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interrupts = <0 16 4>,
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<0 17 4>,
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<0 18 4>,
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<0 19 4>,
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<0 20 4>,
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<0 21 4>,
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<0 22 4>,
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<0 23 4>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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clocks = <&clk>;
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clock-names = "ipg";
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};

‎MAINTAINERS

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F: drivers/pinctrl/aspeed/
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F: Documentation/devicetree/bindings/pinctrl/aspeed,*
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ASPEED SCU INTERRUPT CONTROLLER DRIVER
2708+
M: Eddie James <[email protected]>
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt
2712+
F: drivers/irqchip/irq-aspeed-scu-ic.c
2713+
F: include/dt-bindings/interrupt-controller/aspeed-scu-ic.h
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27072715
ASPEED VIDEO ENGINE DRIVER
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M: Eddie James <[email protected]>
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L: [email protected]

‎arch/arm/include/asm/arch_gicv3.h

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#ifndef __ASSEMBLY__
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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/*
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* GITS_VPROPBASER - hi and lo bits may be accessed independently.
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*/
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#define gits_read_vpropbaser(c) __gic_readq_nonatomic(c)
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#define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
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/*

‎arch/arm/mach-exynos/Kconfig

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@@ -12,6 +12,7 @@ menuconfig ARCH_EXYNOS
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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_AMBA
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select ARM_GIC
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select EXYNOS_IRQ_COMBINER
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select COMMON_CLK_SAMSUNG
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select EXYNOS_ASV
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select EXYNOS_CHIPID

‎arch/arm64/include/asm/arch_gicv3.h

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@@ -141,6 +141,7 @@ static inline u32 gic_read_rpr(void)
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#define gicr_read_pendbaser(c) readq_relaxed(c)
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143143
#define gits_write_vpropbaser(v, c) writeq_relaxed(v, c)
144+
#define gits_read_vpropbaser(c) readq_relaxed(c)
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145146
#define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
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#define gits_read_vpendbaser(c) readq_relaxed(c)

‎drivers/gpio/Kconfig

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@@ -479,6 +479,15 @@ config GPIO_SAMA5D2_PIOBU
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The difference from regular GPIOs is that they
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maintain their value during backup/self-refresh.
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482+
config GPIO_SIFIVE
483+
bool "SiFive GPIO support"
484+
depends on OF_GPIO && IRQ_DOMAIN_HIERARCHY
485+
select GPIO_GENERIC
486+
select GPIOLIB_IRQCHIP
487+
select REGMAP_MMIO
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help
489+
Say yes here to support the GPIO device on SiFive SoCs.
490+
482491
config GPIO_SIOX
483492
tristate "SIOX GPIO support"
484493
depends on SIOX

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