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clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg clock and reset controllers. These provide the base clocks and resets on the platform, enough to bring up all essential blocks including PWRAP, MSDC and peripherals (UART, I2C, SPI). Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎MAINTAINERS

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@@ -14533,6 +14533,10 @@ M: Yassine Oudjana <[email protected]>
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L: [email protected]
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c
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F: drivers/clk/mediatek/clk-mt6735-infracfg.c
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F: drivers/clk/mediatek/clk-mt6735-pericfg.c
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F: drivers/clk/mediatek/clk-mt6735-topckgen.c
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F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
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F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
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F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h

‎drivers/clk/mediatek/Kconfig

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@@ -124,6 +124,15 @@ config COMMON_CLK_MT2712_VENCSYS
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help
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This driver supports MediaTek MT2712 vencsys clocks.
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config COMMON_CLK_MT6735
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tristate "Main clock drivers for MediaTek MT6735"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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help
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This enables drivers for clocks and resets provided
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by apmixedsys, topckgen, infracfg and pericfg on the
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MediaTek MT6735 SoC.
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config COMMON_CLK_MT6765
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bool "Clock driver for MediaTek MT6765"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

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@@ -2,6 +2,7 @@
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obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
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obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
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obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
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obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
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obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
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obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o

‎drivers/clk/mediatek/clk-mt6735-apmixedsys.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <[email protected]>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#include <dt-bindings/clock/mediatek,mt6735-apmixedsys.h>
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#define AP_PLL_CON_5 0x014
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#define ARMPLL_CON0 0x200
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#define ARMPLL_CON1 0x204
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#define ARMPLL_PWR_CON0 0x20c
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#define MAINPLL_CON0 0x210
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#define MAINPLL_CON1 0x214
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#define MAINPLL_PWR_CON0 0x21c
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#define UNIVPLL_CON0 0x220
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#define UNIVPLL_CON1 0x224
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#define UNIVPLL_PWR_CON0 0x22c
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#define MMPLL_CON0 0x230
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#define MMPLL_CON1 0x234
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#define MMPLL_PWR_CON0 0x23c
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#define MSDCPLL_CON0 0x240
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#define MSDCPLL_CON1 0x244
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#define MSDCPLL_PWR_CON0 0x24c
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#define VENCPLL_CON0 0x250
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#define VENCPLL_CON1 0x254
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#define VENCPLL_PWR_CON0 0x25c
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#define TVDPLL_CON0 0x260
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#define TVDPLL_CON1 0x264
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#define TVDPLL_PWR_CON0 0x26c
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#define APLL1_CON0 0x270
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#define APLL1_CON1 0x274
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#define APLL1_CON2 0x278
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#define APLL1_PWR_CON0 0x280
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#define APLL2_CON0 0x284
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#define APLL2_CON1 0x288
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#define APLL2_CON2 0x28c
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#define APLL2_PWR_CON0 0x294
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#define CON0_RST_BAR BIT(24)
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask, \
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_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcwbits, _flags) { \
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.id = _id, \
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.name = _name, \
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.parent_name = "clk26m", \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.rst_bar_mask = _rst_bar_mask, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_chg_reg = _pcw_reg, \
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.pcwbits = _pcwbits, \
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.flags = _flags, \
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}
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static const struct mtk_pll_data apmixedsys_plls[] = {
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PLL(CLK_APMIXED_ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0, 0, 0, ARMPLL_CON1, 21, PLL_AO),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, MAINPLL_PWR_CON0, 0xf0000101, CON0_RST_BAR, MAINPLL_CON1, 24, 0, 0, 0, MAINPLL_CON1, 21, HAVE_RST_BAR),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIVPLL_CON1, 24, 0, 0, 0, UNIVPLL_CON1, 21, HAVE_RST_BAR),
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PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0, MMPLL_PWR_CON0, 0x00000001, 0, MMPLL_CON1, 24, 0, 0, 0, MMPLL_CON1, 21, 0),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x00000001, 0, MSDCPLL_CON1, 24, 0, 0, 0, MSDCPLL_CON1, 21, 0),
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PLL(CLK_APMIXED_VENCPLL, "vencpll", VENCPLL_CON0, VENCPLL_PWR_CON0, 0x00000001, CON0_RST_BAR, VENCPLL_CON1, 24, 0, 0, 0, VENCPLL_CON1, 21, HAVE_RST_BAR),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", TVDPLL_CON0, TVDPLL_PWR_CON0, 0x00000001, 0, TVDPLL_CON1, 24, 0, 0, 0, TVDPLL_CON1, 21, 0),
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PLL(CLK_APMIXED_APLL1, "apll1", APLL1_CON0, APLL1_PWR_CON0, 0x00000001, 0, APLL1_CON0, 4, APLL1_CON2, AP_PLL_CON_5, 0, APLL1_CON1, 31, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0, APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0)
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};
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static int clk_mt6735_apmixed_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct clk_hw_onecell_data *clk_data;
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int ret;
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixedsys_plls));
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if (!clk_data)
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return -ENOMEM;
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platform_set_drvdata(pdev, clk_data);
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ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
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ARRAY_SIZE(apmixedsys_plls), clk_data);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
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return ret;
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}
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ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
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clk_data);
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if (ret)
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dev_err(&pdev->dev,
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"Failed to register clock provider: %d\n", ret);
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return ret;
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}
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static void clk_mt6735_apmixed_remove(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk_data);
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mtk_free_clk_data(clk_data);
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}
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static const struct of_device_id of_match_mt6735_apmixedsys[] = {
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{ .compatible = "mediatek,mt6735-apmixedsys" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_mt6735_apmixedsys);
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static struct platform_driver clk_mt6735_apmixedsys = {
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.probe = clk_mt6735_apmixed_probe,
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.remove = clk_mt6735_apmixed_remove,
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.driver = {
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.name = "clk-mt6735-apmixedsys",
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.of_match_table = of_match_mt6735_apmixedsys,
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},
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};
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module_platform_driver(clk_mt6735_apmixedsys);
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MODULE_AUTHOR("Yassine Oudjana <[email protected]>");
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MODULE_DESCRIPTION("MediaTek MT6735 apmixedsys clock driver");
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MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt6735-infracfg.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <[email protected]>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
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#include <dt-bindings/reset/mediatek,mt6735-infracfg.h>
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#define INFRA_RST0 0x30
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#define INFRA_GLOBALCON_PDN0 0x40
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#define INFRA_PDN1 0x44
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#define INFRA_PDN_STA 0x48
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#define RST_NR_PER_BANK 32
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static struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = INFRA_GLOBALCON_PDN0,
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.clr_ofs = INFRA_PDN1,
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.sta_ofs = INFRA_PDN_STA,
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};
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static const struct mtk_gate infracfg_gates[] = {
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GATE_MTK(CLK_INFRA_DBG, "dbg", "axi_sel", &infra_cg_regs, 0, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_GCE, "gce", "axi_sel", &infra_cg_regs, 1, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_TRBG, "trbg", "axi_sel", &infra_cg_regs, 2, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CPUM, "cpum", "axi_sel", &infra_cg_regs, 3, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_DEVAPC, "devapc", "axi_sel", &infra_cg_regs, 4, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_AUDIO, "audio", "aud_intbus_sel", &infra_cg_regs, 5, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_GCPU, "gcpu", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_L2C_SRAM, "l2csram", "axi_sel", &infra_cg_regs, 7, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_M4U, "m4u", "axi_sel", &infra_cg_regs, 8, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CLDMA, "cldma", "axi_sel", &infra_cg_regs, 12, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CONNMCU_BUS, "connmcu_bus", "axi_sel", &infra_cg_regs, 15, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_KP, "kp", "axi_sel", &infra_cg_regs, 16, &mtk_clk_gate_ops_setclr),
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GATE_MTK_FLAGS(CLK_INFRA_APXGPT, "apxgpt", "axi_sel", &infra_cg_regs, 18, &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL),
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GATE_MTK(CLK_INFRA_SEJ, "sej", "axi_sel", &infra_cg_regs, 19, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CCIF0_AP, "ccif0ap", "axi_sel", &infra_cg_regs, 20, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CCIF1_AP, "ccif1ap", "axi_sel", &infra_cg_regs, 21, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_PMIC_SPI, "pmicspi", "pmicspi_sel", &infra_cg_regs, 22, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_PMIC_WRAP, "pmicwrap", "axi_sel", &infra_cg_regs, 23, &mtk_clk_gate_ops_setclr)
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};
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static u16 infracfg_rst_bank_ofs[] = { INFRA_RST0 };
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static u16 infracfg_rst_idx_map[] = {
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[MT6735_INFRA_RST0_EMI_REG] = 0 * RST_NR_PER_BANK + 0,
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[MT6735_INFRA_RST0_DRAMC0_AO] = 0 * RST_NR_PER_BANK + 1,
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[MT6735_INFRA_RST0_AP_CIRQ_EINT] = 0 * RST_NR_PER_BANK + 3,
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[MT6735_INFRA_RST0_APXGPT] = 0 * RST_NR_PER_BANK + 4,
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[MT6735_INFRA_RST0_SCPSYS] = 0 * RST_NR_PER_BANK + 5,
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[MT6735_INFRA_RST0_KP] = 0 * RST_NR_PER_BANK + 6,
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[MT6735_INFRA_RST0_PMIC_WRAP] = 0 * RST_NR_PER_BANK + 7,
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[MT6735_INFRA_RST0_CLDMA_AO_TOP] = 0 * RST_NR_PER_BANK + 8,
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[MT6735_INFRA_RST0_USBSIF_TOP] = 0 * RST_NR_PER_BANK + 9,
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[MT6735_INFRA_RST0_EMI] = 0 * RST_NR_PER_BANK + 16,
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[MT6735_INFRA_RST0_CCIF] = 0 * RST_NR_PER_BANK + 17,
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[MT6735_INFRA_RST0_DRAMC0] = 0 * RST_NR_PER_BANK + 18,
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[MT6735_INFRA_RST0_EMI_AO_REG] = 0 * RST_NR_PER_BANK + 19,
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[MT6735_INFRA_RST0_CCIF_AO] = 0 * RST_NR_PER_BANK + 20,
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[MT6735_INFRA_RST0_TRNG] = 0 * RST_NR_PER_BANK + 21,
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[MT6735_INFRA_RST0_SYS_CIRQ] = 0 * RST_NR_PER_BANK + 22,
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[MT6735_INFRA_RST0_GCE] = 0 * RST_NR_PER_BANK + 23,
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[MT6735_INFRA_RST0_M4U] = 0 * RST_NR_PER_BANK + 24,
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[MT6735_INFRA_RST0_CCIF1] = 0 * RST_NR_PER_BANK + 25,
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[MT6735_INFRA_RST0_CLDMA_TOP_PD] = 0 * RST_NR_PER_BANK + 26
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};
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static const struct mtk_clk_rst_desc infracfg_resets = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = infracfg_rst_bank_ofs,
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.rst_bank_nr = ARRAY_SIZE(infracfg_rst_bank_ofs),
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.rst_idx_map = infracfg_rst_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(infracfg_rst_idx_map)
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};
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static const struct mtk_clk_desc infracfg_clks = {
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.clks = infracfg_gates,
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.num_clks = ARRAY_SIZE(infracfg_gates),
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.rst_desc = &infracfg_resets
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};
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static const struct of_device_id of_match_mt6735_infracfg[] = {
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{ .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_mt6735_infracfg);
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static struct platform_driver clk_mt6735_infracfg = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-infracfg",
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.of_match_table = of_match_mt6735_infracfg,
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},
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};
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module_platform_driver(clk_mt6735_infracfg);
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MODULE_AUTHOR("Yassine Oudjana <[email protected]>");
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MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
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MODULE_LICENSE("GPL");

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