@@ -59,6 +59,12 @@ static int amdgpu_ih_srcid_jpeg[] = {
59
59
VCN_4_0__SRCID__JPEG7_DECODE
60
60
};
61
61
62
+ static inline bool jpeg_v4_0_3_normalizn_reqd (struct amdgpu_device * adev )
63
+ {
64
+ return amdgpu_sriov_vf (adev ) ||
65
+ (amdgpu_ip_version (adev , GC_HWIP , 0 ) == IP_VERSION (9 , 4 , 4 ));
66
+ }
67
+
62
68
/**
63
69
* jpeg_v4_0_3_early_init - set function pointers
64
70
*
@@ -734,32 +740,20 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
734
740
0 , PACKETJ_CONDITION_CHECK0 , PACKETJ_TYPE4 ));
735
741
amdgpu_ring_write (ring , 0 );
736
742
737
- if (ring -> adev -> jpeg .inst [ring -> me ].aid_id ) {
738
- amdgpu_ring_write (ring , PACKETJ (regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET ,
739
- 0 , PACKETJ_CONDITION_CHECK0 , PACKETJ_TYPE0 ));
740
- amdgpu_ring_write (ring , 0x4 );
741
- } else {
742
- amdgpu_ring_write (ring , PACKETJ (0 , 0 , 0 , PACKETJ_TYPE6 ));
743
- amdgpu_ring_write (ring , 0 );
744
- }
743
+ amdgpu_ring_write (ring , PACKETJ (0 , 0 , 0 , PACKETJ_TYPE6 ));
744
+ amdgpu_ring_write (ring , 0 );
745
745
746
746
amdgpu_ring_write (ring , PACKETJ (regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET ,
747
747
0 , 0 , PACKETJ_TYPE0 ));
748
748
amdgpu_ring_write (ring , 0x3fbc );
749
749
750
- if (ring -> adev -> jpeg .inst [ring -> me ].aid_id ) {
751
- amdgpu_ring_write (ring , PACKETJ (regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET ,
752
- 0 , PACKETJ_CONDITION_CHECK0 , PACKETJ_TYPE0 ));
753
- amdgpu_ring_write (ring , 0x0 );
754
- } else {
755
- amdgpu_ring_write (ring , PACKETJ (0 , 0 , 0 , PACKETJ_TYPE6 ));
756
- amdgpu_ring_write (ring , 0 );
757
- }
758
-
759
750
amdgpu_ring_write (ring , PACKETJ (JRBC_DEC_EXTERNAL_REG_WRITE_ADDR ,
760
751
0 , 0 , PACKETJ_TYPE0 ));
761
752
amdgpu_ring_write (ring , 0x1 );
762
753
754
+ amdgpu_ring_write (ring , PACKETJ (0 , 0 , 0 , PACKETJ_TYPE6 ));
755
+ amdgpu_ring_write (ring , 0 );
756
+
763
757
amdgpu_ring_write (ring , PACKETJ (0 , 0 , 0 , PACKETJ_TYPE7 ));
764
758
amdgpu_ring_write (ring , 0 );
765
759
}
@@ -834,8 +828,8 @@ void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
834
828
{
835
829
uint32_t reg_offset ;
836
830
837
- /* For VF, only local offsets should be used */
838
- if (amdgpu_sriov_vf (ring -> adev ))
831
+ /* Use normalized offsets if required */
832
+ if (jpeg_v4_0_3_normalizn_reqd (ring -> adev ))
839
833
reg = NORMALIZE_JPEG_REG_OFFSET (reg );
840
834
841
835
reg_offset = (reg << 2 );
@@ -881,8 +875,8 @@ void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint
881
875
{
882
876
uint32_t reg_offset ;
883
877
884
- /* For VF, only local offsets should be used */
885
- if (amdgpu_sriov_vf (ring -> adev ))
878
+ /* Use normalized offsets if required */
879
+ if (jpeg_v4_0_3_normalizn_reqd (ring -> adev ))
886
880
reg = NORMALIZE_JPEG_REG_OFFSET (reg );
887
881
888
882
reg_offset = (reg << 2 );
0 commit comments