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Lijo Lazaralexdeucher
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drm/amdgpu: Normalize reg offsets on JPEG v4.0.3
On VFs and SOCs with GC 9.4.4, VCN RRMT is disabled. Only local register offsets should be used on JPEG v4.0.3 as they cannot handle remote access to other AIDs. Since only local offsets are used, the special write to MCM_ADDR register is no longer needed. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Sathishkumar S <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

Lines changed: 15 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,12 @@ static int amdgpu_ih_srcid_jpeg[] = {
5959
VCN_4_0__SRCID__JPEG7_DECODE
6060
};
6161

62+
static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
63+
{
64+
return amdgpu_sriov_vf(adev) ||
65+
(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4));
66+
}
67+
6268
/**
6369
* jpeg_v4_0_3_early_init - set function pointers
6470
*
@@ -734,32 +740,20 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
734740
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
735741
amdgpu_ring_write(ring, 0);
736742

737-
if (ring->adev->jpeg.inst[ring->me].aid_id) {
738-
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
739-
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
740-
amdgpu_ring_write(ring, 0x4);
741-
} else {
742-
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
743-
amdgpu_ring_write(ring, 0);
744-
}
743+
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
744+
amdgpu_ring_write(ring, 0);
745745

746746
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
747747
0, 0, PACKETJ_TYPE0));
748748
amdgpu_ring_write(ring, 0x3fbc);
749749

750-
if (ring->adev->jpeg.inst[ring->me].aid_id) {
751-
amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
752-
0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
753-
amdgpu_ring_write(ring, 0x0);
754-
} else {
755-
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
756-
amdgpu_ring_write(ring, 0);
757-
}
758-
759750
amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
760751
0, 0, PACKETJ_TYPE0));
761752
amdgpu_ring_write(ring, 0x1);
762753

754+
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
755+
amdgpu_ring_write(ring, 0);
756+
763757
amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
764758
amdgpu_ring_write(ring, 0);
765759
}
@@ -834,8 +828,8 @@ void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
834828
{
835829
uint32_t reg_offset;
836830

837-
/* For VF, only local offsets should be used */
838-
if (amdgpu_sriov_vf(ring->adev))
831+
/* Use normalized offsets if required */
832+
if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
839833
reg = NORMALIZE_JPEG_REG_OFFSET(reg);
840834

841835
reg_offset = (reg << 2);
@@ -881,8 +875,8 @@ void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint
881875
{
882876
uint32_t reg_offset;
883877

884-
/* For VF, only local offsets should be used */
885-
if (amdgpu_sriov_vf(ring->adev))
878+
/* Use normalized offsets if required */
879+
if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
886880
reg = NORMALIZE_JPEG_REG_OFFSET(reg);
887881

888882
reg_offset = (reg << 2);

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