|
13 | 13 | * more details.
|
14 | 14 | */
|
15 | 15 |
|
16 |
| -#ifndef __SYSTEM_GLOBAL_H_INCLUDED__ |
17 |
| -#define __SYSTEM_GLOBAL_H_INCLUDED__ |
18 |
| - |
19 |
| -#include <hive_isp_css_defs.h> |
20 |
| -#include <type_support.h> |
21 |
| - |
22 |
| -/* |
23 |
| - * The longest allowed (uninteruptible) bus transfer, does not |
24 |
| - * take stalling into account |
25 |
| - */ |
26 |
| -#define HIVE_ISP_MAX_BURST_LENGTH 1024 |
27 |
| - |
28 |
| -/* |
29 |
| - * Maximum allowed burst length in words for the ISP DMA |
30 |
| - */ |
31 |
| -#define ISP_DMA_MAX_BURST_LENGTH 128 |
32 |
| - |
33 |
| -/* |
34 |
| - * Create a list of HAS and IS properties that defines the system |
35 |
| - * |
36 |
| - * The configuration assumes the following |
37 |
| - * - The system is hetereogeneous; Multiple cells and devices classes |
38 |
| - * - The cell and device instances are homogeneous, each device type |
39 |
| - * belongs to the same class |
40 |
| - * - Device instances supporting a subset of the class capabilities are |
41 |
| - * allowed |
42 |
| - * |
43 |
| - * We could manage different device classes through the enumerated |
44 |
| - * lists (C) or the use of classes (C++), but that is presently not |
45 |
| - * fully supported |
46 |
| - * |
47 |
| - * N.B. the 3 input formatters are of 2 different classess |
48 |
| - */ |
49 |
| - |
50 | 16 | #define USE_INPUT_SYSTEM_VERSION_2
|
51 |
| - |
52 |
| -#define HAS_MMU_VERSION_2 |
53 |
| -#define HAS_DMA_VERSION_2 |
54 |
| -#define HAS_GDC_VERSION_2 |
55 |
| -#define HAS_VAMEM_VERSION_2 |
56 |
| -#define HAS_HMEM_VERSION_1 |
57 |
| -#define HAS_BAMEM_VERSION_2 |
58 |
| -#define HAS_IRQ_VERSION_2 |
59 |
| -#define HAS_IRQ_MAP_VERSION_2 |
60 |
| -#define HAS_INPUT_FORMATTER_VERSION_2 |
61 |
| -/* 2401: HAS_INPUT_SYSTEM_VERSION_2401 */ |
62 |
| -#define HAS_INPUT_SYSTEM_VERSION_2 |
63 |
| -#define HAS_BUFFERED_SENSOR |
64 |
| -#define HAS_FIFO_MONITORS_VERSION_2 |
65 |
| -/* #define HAS_GP_REGS_VERSION_2 */ |
66 |
| -#define HAS_GP_DEVICE_VERSION_2 |
67 |
| -#define HAS_GPIO_VERSION_1 |
68 |
| -#define HAS_TIMED_CTRL_VERSION_1 |
69 |
| -#define HAS_RX_VERSION_2 |
70 |
| - |
71 |
| -#define DMA_DDR_TO_VAMEM_WORKAROUND |
72 |
| -#define DMA_DDR_TO_HMEM_WORKAROUND |
73 |
| - |
74 |
| -/* |
75 |
| - * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply |
76 |
| - */ |
77 |
| -#define HRT_VADDRESS_WIDTH 32 |
78 |
| - |
79 |
| -#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3) |
80 |
| -#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8) |
81 |
| - |
82 |
| -/* The main bus connecting all devices */ |
83 |
| -#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH |
84 |
| -#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES |
85 |
| - |
86 |
| -/* per-frame parameter handling support */ |
87 |
| -#define SH_CSS_ENABLE_PER_FRAME_PARAMS |
88 |
| - |
89 |
| -typedef u32 hrt_bus_align_t; |
90 |
| - |
91 |
| -/* |
92 |
| - * Enumerate the devices, device access through the API is by ID, through the DLI by address |
93 |
| - * The enumerator terminators are used to size the wiring arrays and as an exception value. |
94 |
| - */ |
95 |
| -typedef enum { |
96 |
| - DDR0_ID = 0, |
97 |
| - N_DDR_ID |
98 |
| -} ddr_ID_t; |
99 |
| - |
100 |
| -typedef enum { |
101 |
| - ISP0_ID = 0, |
102 |
| - N_ISP_ID |
103 |
| -} isp_ID_t; |
104 |
| - |
105 |
| -typedef enum { |
106 |
| - SP0_ID = 0, |
107 |
| - N_SP_ID |
108 |
| -} sp_ID_t; |
109 |
| - |
110 |
| -typedef enum { |
111 |
| - MMU0_ID = 0, |
112 |
| - MMU1_ID, |
113 |
| - N_MMU_ID |
114 |
| -} mmu_ID_t; |
115 |
| - |
116 |
| -typedef enum { |
117 |
| - DMA0_ID = 0, |
118 |
| - N_DMA_ID |
119 |
| -} dma_ID_t; |
120 |
| - |
121 |
| -typedef enum { |
122 |
| - GDC0_ID = 0, |
123 |
| - GDC1_ID, |
124 |
| - N_GDC_ID |
125 |
| -} gdc_ID_t; |
126 |
| - |
127 |
| -#define N_GDC_ID_CPP 2 // this extra define is needed because we want to use it also in the preprocessor, and that doesn't work with enums. |
128 |
| - |
129 |
| -typedef enum { |
130 |
| - VAMEM0_ID = 0, |
131 |
| - VAMEM1_ID, |
132 |
| - VAMEM2_ID, |
133 |
| - N_VAMEM_ID |
134 |
| -} vamem_ID_t; |
135 |
| - |
136 |
| -typedef enum { |
137 |
| - BAMEM0_ID = 0, |
138 |
| - N_BAMEM_ID |
139 |
| -} bamem_ID_t; |
140 |
| - |
141 |
| -typedef enum { |
142 |
| - HMEM0_ID = 0, |
143 |
| - N_HMEM_ID |
144 |
| -} hmem_ID_t; |
145 |
| - |
146 |
| -/* |
147 |
| -typedef enum { |
148 |
| - IRQ0_ID = 0, |
149 |
| - N_IRQ_ID |
150 |
| -} irq_ID_t; |
151 |
| -*/ |
152 |
| - |
153 |
| -typedef enum { |
154 |
| - IRQ0_ID = 0, // GP IRQ block |
155 |
| - IRQ1_ID, // Input formatter |
156 |
| - IRQ2_ID, // input system |
157 |
| - IRQ3_ID, // input selector |
158 |
| - N_IRQ_ID |
159 |
| -} irq_ID_t; |
160 |
| - |
161 |
| -typedef enum { |
162 |
| - FIFO_MONITOR0_ID = 0, |
163 |
| - N_FIFO_MONITOR_ID |
164 |
| -} fifo_monitor_ID_t; |
165 |
| - |
166 |
| -/* |
167 |
| - * Deprecated: Since all gp_reg instances are different |
168 |
| - * and put in the address maps of other devices we cannot |
169 |
| - * enumerate them as that assumes the instrances are the |
170 |
| - * same. |
171 |
| - * |
172 |
| - * We define a single GP_DEVICE containing all gp_regs |
173 |
| - * w.r.t. a single base address |
174 |
| - * |
175 |
| -typedef enum { |
176 |
| - GP_REGS0_ID = 0, |
177 |
| - N_GP_REGS_ID |
178 |
| -} gp_regs_ID_t; |
179 |
| - */ |
180 |
| -typedef enum { |
181 |
| - GP_DEVICE0_ID = 0, |
182 |
| - N_GP_DEVICE_ID |
183 |
| -} gp_device_ID_t; |
184 |
| - |
185 |
| -typedef enum { |
186 |
| - GP_TIMER0_ID = 0, |
187 |
| - GP_TIMER1_ID, |
188 |
| - GP_TIMER2_ID, |
189 |
| - GP_TIMER3_ID, |
190 |
| - GP_TIMER4_ID, |
191 |
| - GP_TIMER5_ID, |
192 |
| - GP_TIMER6_ID, |
193 |
| - GP_TIMER7_ID, |
194 |
| - N_GP_TIMER_ID |
195 |
| -} gp_timer_ID_t; |
196 |
| - |
197 |
| -typedef enum { |
198 |
| - GPIO0_ID = 0, |
199 |
| - N_GPIO_ID |
200 |
| -} gpio_ID_t; |
201 |
| - |
202 |
| -typedef enum { |
203 |
| - TIMED_CTRL0_ID = 0, |
204 |
| - N_TIMED_CTRL_ID |
205 |
| -} timed_ctrl_ID_t; |
206 |
| - |
207 |
| -typedef enum { |
208 |
| - INPUT_FORMATTER0_ID = 0, |
209 |
| - INPUT_FORMATTER1_ID, |
210 |
| - INPUT_FORMATTER2_ID, |
211 |
| - INPUT_FORMATTER3_ID, |
212 |
| - N_INPUT_FORMATTER_ID |
213 |
| -} input_formatter_ID_t; |
214 |
| - |
215 |
| -/* The IF RST is outside the IF */ |
216 |
| -#define INPUT_FORMATTER0_SRST_OFFSET 0x0824 |
217 |
| -#define INPUT_FORMATTER1_SRST_OFFSET 0x0624 |
218 |
| -#define INPUT_FORMATTER2_SRST_OFFSET 0x0424 |
219 |
| -#define INPUT_FORMATTER3_SRST_OFFSET 0x0224 |
220 |
| - |
221 |
| -#define INPUT_FORMATTER0_SRST_MASK 0x0001 |
222 |
| -#define INPUT_FORMATTER1_SRST_MASK 0x0002 |
223 |
| -#define INPUT_FORMATTER2_SRST_MASK 0x0004 |
224 |
| -#define INPUT_FORMATTER3_SRST_MASK 0x0008 |
225 |
| - |
226 |
| -typedef enum { |
227 |
| - INPUT_SYSTEM0_ID = 0, |
228 |
| - N_INPUT_SYSTEM_ID |
229 |
| -} input_system_ID_t; |
230 |
| - |
231 |
| -typedef enum { |
232 |
| - RX0_ID = 0, |
233 |
| - N_RX_ID |
234 |
| -} rx_ID_t; |
235 |
| - |
236 |
| -enum mipi_port_id { |
237 |
| - MIPI_PORT0_ID = 0, |
238 |
| - MIPI_PORT1_ID, |
239 |
| - MIPI_PORT2_ID, |
240 |
| - N_MIPI_PORT_ID |
241 |
| -}; |
242 |
| - |
243 |
| -#define N_RX_CHANNEL_ID 4 |
244 |
| - |
245 |
| -/* Generic port enumeration with an internal port type ID */ |
246 |
| -typedef enum { |
247 |
| - CSI_PORT0_ID = 0, |
248 |
| - CSI_PORT1_ID, |
249 |
| - CSI_PORT2_ID, |
250 |
| - TPG_PORT0_ID, |
251 |
| - PRBS_PORT0_ID, |
252 |
| - FIFO_PORT0_ID, |
253 |
| - MEMORY_PORT0_ID, |
254 |
| - N_INPUT_PORT_ID |
255 |
| -} input_port_ID_t; |
256 |
| - |
257 |
| -typedef enum { |
258 |
| - CAPTURE_UNIT0_ID = 0, |
259 |
| - CAPTURE_UNIT1_ID, |
260 |
| - CAPTURE_UNIT2_ID, |
261 |
| - ACQUISITION_UNIT0_ID, |
262 |
| - DMA_UNIT0_ID, |
263 |
| - CTRL_UNIT0_ID, |
264 |
| - GPREGS_UNIT0_ID, |
265 |
| - FIFO_UNIT0_ID, |
266 |
| - IRQ_UNIT0_ID, |
267 |
| - N_SUB_SYSTEM_ID |
268 |
| -} sub_system_ID_t; |
269 |
| - |
270 |
| -#define N_CAPTURE_UNIT_ID 3 |
271 |
| -#define N_ACQUISITION_UNIT_ID 1 |
272 |
| -#define N_CTRL_UNIT_ID 1 |
273 |
| - |
274 |
| -enum ia_css_isp_memories { |
275 |
| - IA_CSS_ISP_PMEM0 = 0, |
276 |
| - IA_CSS_ISP_DMEM0, |
277 |
| - IA_CSS_ISP_VMEM0, |
278 |
| - IA_CSS_ISP_VAMEM0, |
279 |
| - IA_CSS_ISP_VAMEM1, |
280 |
| - IA_CSS_ISP_VAMEM2, |
281 |
| - IA_CSS_ISP_HMEM0, |
282 |
| - IA_CSS_SP_DMEM0, |
283 |
| - IA_CSS_DDR, |
284 |
| - N_IA_CSS_MEMORIES |
285 |
| -}; |
286 |
| - |
287 |
| -#define IA_CSS_NUM_MEMORIES 9 |
288 |
| -/* For driver compatibility */ |
289 |
| -#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES |
290 |
| -#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES |
291 |
| - |
292 |
| -#if 0 |
293 |
| -typedef enum { |
294 |
| - dev_chn, /* device channels, external resource */ |
295 |
| - ext_mem, /* external memories */ |
296 |
| - int_mem, /* internal memories */ |
297 |
| - int_chn /* internal channels, user defined */ |
298 |
| -} resource_type_t; |
299 |
| - |
300 |
| -/* if this enum is extended with other memory resources, pls also extend the function resource_to_memptr() */ |
301 |
| -typedef enum { |
302 |
| - vied_nci_dev_chn_dma_ext0, |
303 |
| - int_mem_vmem0, |
304 |
| - int_mem_dmem0 |
305 |
| -} resource_id_t; |
306 |
| - |
307 |
| -/* enum listing the different memories within a program group. |
308 |
| - This enum is used in the mem_ptr_t type */ |
309 |
| -typedef enum { |
310 |
| - buf_mem_invalid = 0, |
311 |
| - buf_mem_vmem_prog0, |
312 |
| - buf_mem_dmem_prog0 |
313 |
| -} buf_mem_t; |
314 |
| - |
315 |
| -#endif |
316 |
| -#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */ |
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