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clocksource/drivers/realtek: Add timer driver for rtl-otto platforms
The timer/counter block on the Realtek SoCs provides up to 5 timers. It also includes a watchdog timer which is handled by the realtek_otto_wdt.c driver. One timer will be used per CPU as a local clock event generator. An additional timer will be used as an overal stable clocksource. Signed-off-by: Markus Stockhausen <[email protected]> Signed-off-by: Sander Vanheule <[email protected]> Signed-off-by: Chris Packham <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Daniel Lezcano <[email protected]>
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‎drivers/clocksource/Kconfig

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@@ -134,6 +134,16 @@ config RDA_TIMER
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help
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Enables the support for the RDA Micro timer driver.
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config REALTEK_OTTO_TIMER
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bool "Clocksource/timer for the Realtek Otto platform" if COMPILE_TEST
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select TIMER_OF
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help
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This driver adds support for the timers found in the Realtek RTL83xx
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and RTL93xx SoCs series. This includes chips such as RTL8380, RTL8381
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and RTL832, as well as chips from the RTL839x series, such as RTL8390
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RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series
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such as RTL9301, RTL9302 or RTL9303.
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config SUN4I_TIMER
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bool "Sun4i timer driver" if COMPILE_TEST
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depends on HAS_IOMEM

‎drivers/clocksource/Makefile

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@@ -59,6 +59,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
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obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
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obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
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obj-$(CONFIG_RDA_TIMER) += timer-rda.o
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obj-$(CONFIG_REALTEK_OTTO_TIMER) += timer-rtl-otto.o
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obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o

‎drivers/clocksource/timer-rtl-otto.c

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@@ -0,0 +1,291 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/cpuhotplug.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/printk.h>
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#include <linux/sched_clock.h>
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#include "timer-of.h"
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#define RTTM_DATA 0x0
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#define RTTM_CNT 0x4
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#define RTTM_CTRL 0x8
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#define RTTM_INT 0xc
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#define RTTM_CTRL_ENABLE BIT(28)
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#define RTTM_INT_PENDING BIT(16)
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#define RTTM_INT_ENABLE BIT(20)
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/*
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* The Otto platform provides multiple 28 bit timers/counters with the following
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* operating logic. If enabled the timer counts up. Per timer one can set a
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* maximum counter value as an end marker. If end marker is reached the timer
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* fires an interrupt. If the timer "overflows" by reaching the end marker or
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* by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and
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* the timer is in operating mode COUNTER it stops. In mode TIMER it will
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* continue to count up.
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*/
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#define RTTM_CTRL_COUNTER 0
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#define RTTM_CTRL_TIMER BIT(24)
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#define RTTM_BIT_COUNT 28
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#define RTTM_MIN_DELTA 8
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#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28)
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/*
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* Timers are derived from the LXB clock frequency. Usually this is a fixed
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* multiple of the 25 MHz oscillator. The 930X SOC is an exception from that.
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* Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its
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* base. The only meaningful frequencies we can achieve from that are 175.000
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* MHz and 153.125 MHz. The greatest common divisor of all explained possible
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* speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
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*/
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#define RTTM_TICKS_PER_SEC 3125000
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struct rttm_cs {
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struct timer_of to;
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struct clocksource cs;
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};
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/* Simple internal register functions */
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static inline void rttm_set_counter(void __iomem *base, unsigned int counter)
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{
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iowrite32(counter, base + RTTM_CNT);
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}
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static inline unsigned int rttm_get_counter(void __iomem *base)
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{
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return ioread32(base + RTTM_CNT);
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}
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static inline void rttm_set_period(void __iomem *base, unsigned int period)
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{
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iowrite32(period, base + RTTM_DATA);
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}
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static inline void rttm_disable_timer(void __iomem *base)
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{
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iowrite32(0, base + RTTM_CTRL);
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}
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static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor)
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{
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iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL);
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}
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static inline void rttm_ack_irq(void __iomem *base)
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{
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iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT);
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}
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static inline void rttm_enable_irq(void __iomem *base)
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{
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iowrite32(RTTM_INT_ENABLE, base + RTTM_INT);
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}
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static inline void rttm_disable_irq(void __iomem *base)
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{
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iowrite32(0, base + RTTM_INT);
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}
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/* Aggregated control functions for kernel clock framework */
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#define RTTM_DEBUG(base) \
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pr_debug("------------- %d %p\n", \
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smp_processor_id(), base)
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static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *clkevt = dev_id;
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struct timer_of *to = to_timer_of(clkevt);
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rttm_ack_irq(to->of_base.base);
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RTTM_DEBUG(to->of_base.base);
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clkevt->event_handler(clkevt);
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return IRQ_HANDLED;
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}
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static void rttm_stop_timer(void __iomem *base)
116+
{
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rttm_disable_timer(base);
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rttm_ack_irq(base);
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}
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static void rttm_start_timer(struct timer_of *to, u32 mode)
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{
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rttm_set_counter(to->of_base.base, 0);
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rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC);
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}
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static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt)
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{
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struct timer_of *to = to_timer_of(clkevt);
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RTTM_DEBUG(to->of_base.base);
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rttm_stop_timer(to->of_base.base);
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rttm_set_period(to->of_base.base, delta);
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rttm_start_timer(to, RTTM_CTRL_COUNTER);
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return 0;
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}
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static int rttm_state_oneshot(struct clock_event_device *clkevt)
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{
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struct timer_of *to = to_timer_of(clkevt);
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RTTM_DEBUG(to->of_base.base);
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rttm_stop_timer(to->of_base.base);
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rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
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rttm_start_timer(to, RTTM_CTRL_COUNTER);
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return 0;
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}
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static int rttm_state_periodic(struct clock_event_device *clkevt)
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{
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struct timer_of *to = to_timer_of(clkevt);
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RTTM_DEBUG(to->of_base.base);
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rttm_stop_timer(to->of_base.base);
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rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
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rttm_start_timer(to, RTTM_CTRL_TIMER);
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return 0;
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}
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static int rttm_state_shutdown(struct clock_event_device *clkevt)
164+
{
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struct timer_of *to = to_timer_of(clkevt);
166+
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RTTM_DEBUG(to->of_base.base);
168+
rttm_stop_timer(to->of_base.base);
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170+
return 0;
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}
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static void rttm_setup_timer(void __iomem *base)
174+
{
175+
RTTM_DEBUG(base);
176+
rttm_stop_timer(base);
177+
rttm_set_period(base, 0);
178+
}
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static u64 rttm_read_clocksource(struct clocksource *cs)
181+
{
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struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
183+
184+
return rttm_get_counter(rcs->to.of_base.base);
185+
}
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/* Module initialization part. */
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static DEFINE_PER_CPU(struct timer_of, rttm_to) = {
189+
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ,
190+
.of_irq = {
191+
.flags = IRQF_PERCPU | IRQF_TIMER,
192+
.handler = rttm_timer_interrupt,
193+
},
194+
.clkevt = {
195+
.rating = 400,
196+
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
197+
.set_state_periodic = rttm_state_periodic,
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.set_state_shutdown = rttm_state_shutdown,
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.set_state_oneshot = rttm_state_oneshot,
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.set_next_event = rttm_next_event
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},
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};
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static int rttm_enable_clocksource(struct clocksource *cs)
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{
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struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
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rttm_disable_irq(rcs->to.of_base.base);
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rttm_setup_timer(rcs->to.of_base.base);
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rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER,
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rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC);
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return 0;
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}
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struct rttm_cs rttm_cs = {
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.to = {
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.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
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},
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.cs = {
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.name = "realtek_otto_timer",
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.rating = 400,
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.mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT),
224+
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = rttm_read_clocksource,
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}
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};
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static u64 notrace rttm_read_clock(void)
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{
231+
return rttm_get_counter(rttm_cs.to.of_base.base);
232+
}
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static int rttm_cpu_starting(unsigned int cpu)
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{
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struct timer_of *to = per_cpu_ptr(&rttm_to, cpu);
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238+
RTTM_DEBUG(to->of_base.base);
239+
to->clkevt.cpumask = cpumask_of(cpu);
240+
irq_force_affinity(to->of_irq.irq, to->clkevt.cpumask);
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clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC,
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RTTM_MIN_DELTA, RTTM_MAX_DELTA);
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rttm_enable_irq(to->of_base.base);
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return 0;
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}
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static int __init rttm_probe(struct device_node *np)
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{
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unsigned int cpu, cpu_rollback;
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struct timer_of *to;
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unsigned int clkidx = num_possible_cpus();
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/* Use the first n timers as per CPU clock event generators */
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for_each_possible_cpu(cpu) {
256+
to = per_cpu_ptr(&rttm_to, cpu);
257+
to->of_irq.index = to->of_base.index = cpu;
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if (timer_of_init(np, to)) {
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pr_err("setup of timer %d failed\n", cpu);
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goto rollback;
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}
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rttm_setup_timer(to->of_base.base);
263+
}
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/* Activate the n'th + 1 timer as a stable CPU clocksource. */
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to = &rttm_cs.to;
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to->of_base.index = clkidx;
268+
timer_of_init(np, to);
269+
if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) {
270+
rttm_enable_clocksource(&rttm_cs.cs);
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clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC);
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sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC);
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} else
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pr_err(" setup of timer %d as clocksource failed", clkidx);
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return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING,
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"timer/realtek:online",
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rttm_cpu_starting, NULL);
279+
rollback:
280+
pr_err("timer registration failed\n");
281+
for_each_possible_cpu(cpu_rollback) {
282+
if (cpu_rollback == cpu)
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break;
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to = per_cpu_ptr(&rttm_to, cpu_rollback);
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timer_of_cleanup(to);
286+
}
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return -EINVAL;
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}
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TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe);

‎include/linux/cpuhotplug.h

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@@ -171,6 +171,7 @@ enum cpuhp_state {
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CPUHP_AP_ARMADA_TIMER_STARTING,
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CPUHP_AP_MIPS_GIC_TIMER_STARTING,
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CPUHP_AP_ARC_TIMER_STARTING,
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CPUHP_AP_REALTEK_TIMER_STARTING,
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CPUHP_AP_RISCV_TIMER_STARTING,
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CPUHP_AP_CLINT_TIMER_STARTING,
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CPUHP_AP_CSKY_TIMER_STARTING,

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