@@ -384,6 +384,19 @@ static void rockchip_spi_dma_txcb(void *data)
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spi_finalize_current_transfer (ctlr );
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}
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+ static u32 rockchip_spi_calc_burst_size (u32 data_len )
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+ {
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+ u32 i ;
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+
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+ /* burst size: 1, 2, 4, 8 */
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+ for (i = 1 ; i < 8 ; i <<= 1 ) {
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+ if (data_len & i )
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+ break ;
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+ }
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+
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+ return i ;
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+ }
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+
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static int rockchip_spi_prepare_dma (struct rockchip_spi * rs ,
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struct spi_controller * ctlr , struct spi_transfer * xfer )
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{
@@ -397,7 +410,8 @@ static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
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.direction = DMA_DEV_TO_MEM ,
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.src_addr = rs -> dma_addr_rx ,
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.src_addr_width = rs -> n_bytes ,
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- .src_maxburst = 1 ,
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+ .src_maxburst = rockchip_spi_calc_burst_size (xfer -> len /
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+ rs -> n_bytes ),
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};
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dmaengine_slave_config (ctlr -> dma_rx , & rxconf );
@@ -525,7 +539,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs,
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writel_relaxed (rs -> fifo_len / 2 - 1 , rs -> regs + ROCKCHIP_SPI_RXFTLR );
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writel_relaxed (rs -> fifo_len / 2 , rs -> regs + ROCKCHIP_SPI_DMATDLR );
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- writel_relaxed (0 , rs -> regs + ROCKCHIP_SPI_DMARDLR );
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+ writel_relaxed (rockchip_spi_calc_burst_size (xfer -> len / rs -> n_bytes ) - 1 ,
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+ rs -> regs + ROCKCHIP_SPI_DMARDLR );
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writel_relaxed (dmacr , rs -> regs + ROCKCHIP_SPI_DMACR );
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/* the hardware only supports an even clock divisor, so
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