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geertugeertu
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pinctrl: renesas: r8a779g0: Fix (H)SCIF3 suffixes
(H)SCIF instance 3 has two alternate pin groups: "hscif3" and "hscif3_a", resp. "scif3" and "scif3_a", but the actual meanings of the pins within the groups do not match. Increase uniformity by adopting R-Car V4M naming: - Rename "hscif3_a" to "hscif3_b", - Rename "hscif3" to "hscif3_a", - Rename "scif3" to "scif3_b". While at it, remove unneeded separators. Fixes: ad9bb2f ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442a ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: 213b713 ("pinctrl: renesas: r8a779g0: Add missing HSCIF3_A") Fixes: 49e4697 ("pinctrl: renesas: r8a779g0: Add missing SCIF3") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/61fdde58e369e8070ffd3c5811c089e6219c7ecc.1717754960.git.geert+renesas@glider.be
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‎drivers/pinctrl/renesas/pfc-r8a779g0.c

Lines changed: 94 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -77,11 +77,11 @@
7777
#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
7878

7979
/* GPSR1 */
80-
#define GPSR1_28 F_(HTX3, IP3SR1_19_16)
81-
#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
82-
#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
83-
#define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
84-
#define GPSR1_24 F_(HRX3, IP3SR1_3_0)
80+
#define GPSR1_28 F_(HTX3_A, IP3SR1_19_16)
81+
#define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12)
82+
#define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8)
83+
#define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4)
84+
#define GPSR1_24 F_(HRX3_A, IP3SR1_3_0)
8585
#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
8686
#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
8787
#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
@@ -301,11 +301,11 @@
301301

302302
/* SR1 */
303303
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
304-
#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305-
#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306-
#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307-
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308-
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304+
#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305+
#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306+
#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307+
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308+
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309309
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310310
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311311
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -331,11 +331,11 @@
331331
#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332332

333333
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
334-
#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335-
#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336-
#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337-
#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338-
#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334+
#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335+
#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336+
#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337+
#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338+
#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339339

340340
/* SR2 */
341341
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -776,24 +776,24 @@ static const u16 pinmux_data[] = {
776776

777777
/* IP0SR1 */
778778
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
779-
PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
780-
PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
779+
PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),
780+
PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),
781781

782782
PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
783-
PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A),
784-
PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
783+
PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),
784+
PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),
785785

786786
PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
787-
PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A),
788-
PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
787+
PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),
788+
PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),
789789

790790
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
791-
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
792-
PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
791+
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
792+
PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
793793

794794
PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
795-
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
796-
PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
795+
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),
796+
PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),
797797

798798
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
799799

@@ -864,25 +864,25 @@ static const u16 pinmux_data[] = {
864864
PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
865865

866866
/* IP3SR1 */
867-
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
867+
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),
868868
PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
869869
PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
870870

871-
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
871+
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
872872
PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
873873
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
874874
PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
875875

876-
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
876+
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
877877
PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
878878
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
879879
PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
880880

881-
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
881+
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
882882
PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
883883
PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
884884

885-
PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
885+
PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),
886886
PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
887887
PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
888888

@@ -1666,49 +1666,48 @@ static const unsigned int hscif2_ctrl_mux[] = {
16661666
};
16671667

16681668
/* - HSCIF3 ----------------------------------------------------------------- */
1669-
static const unsigned int hscif3_data_pins[] = {
1670-
/* HRX3, HTX3 */
1669+
static const unsigned int hscif3_data_a_pins[] = {
1670+
/* HRX3_A, HTX3_A */
16711671
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
16721672
};
1673-
static const unsigned int hscif3_data_mux[] = {
1674-
HRX3_MARK, HTX3_MARK,
1673+
static const unsigned int hscif3_data_a_mux[] = {
1674+
HRX3_A_MARK, HTX3_A_MARK,
16751675
};
1676-
static const unsigned int hscif3_clk_pins[] = {
1677-
/* HSCK3 */
1676+
static const unsigned int hscif3_clk_a_pins[] = {
1677+
/* HSCK3_A */
16781678
RCAR_GP_PIN(1, 25),
16791679
};
1680-
static const unsigned int hscif3_clk_mux[] = {
1681-
HSCK3_MARK,
1680+
static const unsigned int hscif3_clk_a_mux[] = {
1681+
HSCK3_A_MARK,
16821682
};
1683-
static const unsigned int hscif3_ctrl_pins[] = {
1684-
/* HRTS3_N, HCTS3_N */
1683+
static const unsigned int hscif3_ctrl_a_pins[] = {
1684+
/* HRTS3_N_A, HCTS3_N_A */
16851685
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
16861686
};
1687-
static const unsigned int hscif3_ctrl_mux[] = {
1688-
HRTS3_N_MARK, HCTS3_N_MARK,
1687+
static const unsigned int hscif3_ctrl_a_mux[] = {
1688+
HRTS3_N_A_MARK, HCTS3_N_A_MARK,
16891689
};
16901690

1691-
/* - HSCIF3_A ----------------------------------------------------------------- */
1692-
static const unsigned int hscif3_data_a_pins[] = {
1693-
/* HRX3_A, HTX3_A */
1691+
static const unsigned int hscif3_data_b_pins[] = {
1692+
/* HRX3_B, HTX3_B */
16941693
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
16951694
};
1696-
static const unsigned int hscif3_data_a_mux[] = {
1697-
HRX3_A_MARK, HTX3_A_MARK,
1695+
static const unsigned int hscif3_data_b_mux[] = {
1696+
HRX3_B_MARK, HTX3_B_MARK,
16981697
};
1699-
static const unsigned int hscif3_clk_a_pins[] = {
1700-
/* HSCK3_A */
1698+
static const unsigned int hscif3_clk_b_pins[] = {
1699+
/* HSCK3_B */
17011700
RCAR_GP_PIN(1, 3),
17021701
};
1703-
static const unsigned int hscif3_clk_a_mux[] = {
1704-
HSCK3_A_MARK,
1702+
static const unsigned int hscif3_clk_b_mux[] = {
1703+
HSCK3_B_MARK,
17051704
};
1706-
static const unsigned int hscif3_ctrl_a_pins[] = {
1707-
/* HRTS3_N_A, HCTS3_N_A */
1705+
static const unsigned int hscif3_ctrl_b_pins[] = {
1706+
/* HRTS3_N_B, HCTS3_N_B */
17081707
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
17091708
};
1710-
static const unsigned int hscif3_ctrl_a_mux[] = {
1711-
HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1709+
static const unsigned int hscif3_ctrl_b_mux[] = {
1710+
HRTS3_N_B_MARK, HCTS3_N_B_MARK,
17121711
};
17131712

17141713
/* - I2C0 ------------------------------------------------------------------- */
@@ -2304,29 +2303,6 @@ static const unsigned int scif1_ctrl_b_mux[] = {
23042303
};
23052304

23062305
/* - SCIF3 ------------------------------------------------------------------ */
2307-
static const unsigned int scif3_data_pins[] = {
2308-
/* RX3, TX3 */
2309-
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2310-
};
2311-
static const unsigned int scif3_data_mux[] = {
2312-
RX3_MARK, TX3_MARK,
2313-
};
2314-
static const unsigned int scif3_clk_pins[] = {
2315-
/* SCK3 */
2316-
RCAR_GP_PIN(1, 4),
2317-
};
2318-
static const unsigned int scif3_clk_mux[] = {
2319-
SCK3_MARK,
2320-
};
2321-
static const unsigned int scif3_ctrl_pins[] = {
2322-
/* RTS3_N, CTS3_N */
2323-
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2324-
};
2325-
static const unsigned int scif3_ctrl_mux[] = {
2326-
RTS3_N_MARK, CTS3_N_MARK,
2327-
};
2328-
2329-
/* - SCIF3_A ------------------------------------------------------------------ */
23302306
static const unsigned int scif3_data_a_pins[] = {
23312307
/* RX3_A, TX3_A */
23322308
RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
@@ -2349,6 +2325,28 @@ static const unsigned int scif3_ctrl_a_mux[] = {
23492325
RTS3_N_A_MARK, CTS3_N_A_MARK,
23502326
};
23512327

2328+
static const unsigned int scif3_data_b_pins[] = {
2329+
/* RX3_B, TX3_B */
2330+
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2331+
};
2332+
static const unsigned int scif3_data_b_mux[] = {
2333+
RX3_B_MARK, TX3_B_MARK,
2334+
};
2335+
static const unsigned int scif3_clk_b_pins[] = {
2336+
/* SCK3_B */
2337+
RCAR_GP_PIN(1, 4),
2338+
};
2339+
static const unsigned int scif3_clk_b_mux[] = {
2340+
SCK3_B_MARK,
2341+
};
2342+
static const unsigned int scif3_ctrl_b_pins[] = {
2343+
/* RTS3_N_B, CTS3_N_B */
2344+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2345+
};
2346+
static const unsigned int scif3_ctrl_b_mux[] = {
2347+
RTS3_N_B_MARK, CTS3_N_B_MARK,
2348+
};
2349+
23522350
/* - SCIF4 ------------------------------------------------------------------ */
23532351
static const unsigned int scif4_data_pins[] = {
23542352
/* RX4, TX4 */
@@ -2593,12 +2591,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
25932591
SH_PFC_PIN_GROUP(hscif2_data),
25942592
SH_PFC_PIN_GROUP(hscif2_clk),
25952593
SH_PFC_PIN_GROUP(hscif2_ctrl),
2596-
SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */
2597-
SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */
2598-
SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */
2599-
SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */
2600-
SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */
2601-
SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */
2594+
SH_PFC_PIN_GROUP(hscif3_data_a),
2595+
SH_PFC_PIN_GROUP(hscif3_clk_a),
2596+
SH_PFC_PIN_GROUP(hscif3_ctrl_a),
2597+
SH_PFC_PIN_GROUP(hscif3_data_b),
2598+
SH_PFC_PIN_GROUP(hscif3_clk_b),
2599+
SH_PFC_PIN_GROUP(hscif3_ctrl_b),
26022600

26032601
SH_PFC_PIN_GROUP(i2c0),
26042602
SH_PFC_PIN_GROUP(i2c1),
@@ -2689,12 +2687,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
26892687
SH_PFC_PIN_GROUP(scif1_data_b),
26902688
SH_PFC_PIN_GROUP(scif1_clk_b),
26912689
SH_PFC_PIN_GROUP(scif1_ctrl_b),
2692-
SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */
2693-
SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */
2694-
SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */
2695-
SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */
2696-
SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */
2697-
SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */
2690+
SH_PFC_PIN_GROUP(scif3_data_a),
2691+
SH_PFC_PIN_GROUP(scif3_clk_a),
2692+
SH_PFC_PIN_GROUP(scif3_ctrl_a),
2693+
SH_PFC_PIN_GROUP(scif3_data_b),
2694+
SH_PFC_PIN_GROUP(scif3_clk_b),
2695+
SH_PFC_PIN_GROUP(scif3_ctrl_b),
26982696
SH_PFC_PIN_GROUP(scif4_data),
26992697
SH_PFC_PIN_GROUP(scif4_clk),
27002698
SH_PFC_PIN_GROUP(scif4_ctrl),
@@ -2823,13 +2821,12 @@ static const char * const hscif2_groups[] = {
28232821
};
28242822

28252823
static const char * const hscif3_groups[] = {
2826-
/* suffix might be updated */
2827-
"hscif3_data",
2828-
"hscif3_clk",
2829-
"hscif3_ctrl",
28302824
"hscif3_data_a",
28312825
"hscif3_clk_a",
28322826
"hscif3_ctrl_a",
2827+
"hscif3_data_b",
2828+
"hscif3_clk_b",
2829+
"hscif3_ctrl_b",
28332830
};
28342831

28352832
static const char * const i2c0_groups[] = {
@@ -2999,13 +2996,12 @@ static const char * const scif1_groups[] = {
29992996
};
30002997

30012998
static const char * const scif3_groups[] = {
3002-
/* suffix might be updated */
3003-
"scif3_data",
3004-
"scif3_clk",
3005-
"scif3_ctrl",
30062999
"scif3_data_a",
30073000
"scif3_clk_a",
30083001
"scif3_ctrl_a",
3002+
"scif3_data_b",
3003+
"scif3_clk_b",
3004+
"scif3_ctrl_b",
30093005
};
30103006

30113007
static const char * const scif4_groups[] = {

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