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Merge branches 'clk-qcom', 'clk-rockchip', 'clk-sophgo' and 'clk-thead' into clk-next
- Add support for the AP sub-system clock controller in the T-Head TH1520 * clk-qcom: (71 commits) clk: qcom: Park shared RCGs upon registration clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks clk: qcom: common: Add interconnect clocks support interconnect: icc-clk: Add devm_icc_clk_register interconnect: icc-clk: Specify master/slave ids dt-bindings: clock: qcom: Add AHB clock for SM8150 clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks clk: qcom: gcc-ipq6018: update sdcc max clock frequency clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver dt-bindings: clock: qcom: Add SM8650 camera clock controller dt-bindings: clock: qcom: Update the order of SC8280XP camcc header clk: qcom: videocc-sm8550: Add SM8650 video clock controller clk: qcom: videocc-sm8550: Add support for videocc XO clk ares dt-bindings: clock: qcom: Add SM8650 video clock controller dt-bindings: clock: qcom: Update SM8450 videocc header file name clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's ... * clk-rockchip: dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKS clk: rockchip: rk3188: Drop CLK_NR_CLKS usage clk: rockchip: Switch to use kmemdup_array() clk: rockchip: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Drop CLK_NR_CLKS clk: rockchip: rk3128: Drop CLK_NR_CLKS usage clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks clk: rockchip: rk3128: Export PCLK_MIPIPHY dt-bindings: clock: rk3128: Add PCLK_MIPIPHY * clk-sophgo: clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate() clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id() clk: sophgo: Add SG2042 clock driver dt-bindings: clock: sophgo: add clkgen for SG2042 dt-bindings: clock: sophgo: add RP gate clocks for SG2042 dt-bindings: clock: sophgo: add pll clocks for SG2042 * clk-thead: clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
5 parents bc060e6 + 691a018 + 04718d1 + 00c7ded + ae81b69 commit 589eb11

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Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml

Lines changed: 4 additions & 16 deletions
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@@ -40,31 +40,19 @@ properties:
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- description: DSI 1 PLL byte clock
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- description: DSI 1 PLL DSI clock
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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power-domains:
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items:
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- description: MMCX power domain
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |

Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |

Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml

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- qcom,sm8350-dispcc
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clocks:
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minItems: 7
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items:
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- description: Board XO source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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- description: Link clock from eDP PHY
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- description: VCO DIV clock from eDP PHY
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- description: Link clock from DP1 PHY
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- description: VCO DIV clock from DP1 PHY
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- description: Link clock from DP2 PHY
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- description: VCO DIV clock from DP2 PHY
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clock-names:
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minItems: 7
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items:
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- const: bi_tcxo
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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- const: edp_phy_pll_link_clk
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- const: edp_phy_pll_vco_div_clk
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- const: dptx1_phy_pll_link_clk
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- const: dptx1_phy_pll_vco_div_clk
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- const: dptx2_phy_pll_link_clk
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- const: dptx2_phy_pll_vco_div_clk
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power-domains:
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description:
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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not:
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properties:
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compatible:
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contains:
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const: qcom,sc8180x-dispcc
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then:
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properties:
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clocks:
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maxItems: 7
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clock-names:
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maxItems: 7
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unevaluatedProperties: false
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examples:
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- |

Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml

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const: 1
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deprecated: true
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'#power-domain-cells': false
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- compatible
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reg = <0x00900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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thermal-sensor {
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compatible = "qcom,msm8960-tsens";

Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml

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required:
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- compatible
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- '#power-domain-cells'
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unevaluatedProperties: false
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Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml

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- const: xo
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'#power-domain-cells': false
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reg = <0x1800000 0x60000>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";

Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml

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- const: xo
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- const: sleep_clk
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'#power-domain-cells': false
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- compatible
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- clocks
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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...

Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml

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- $ref: /schemas/thermal/qcom-tsens.yaml#
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'#power-domain-cells': false
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- compatible
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- clocks
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clock-names = "pxo", "cxo", "pll4";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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tsens: thermal-sensor {
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compatible = "qcom,ipq8064-tsens";

Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml

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- compatible
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- '#power-domain-cells'
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unevaluatedProperties: false
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Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml renamed to Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml

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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
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$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller
@@ -15,7 +15,6 @@ description: |
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domains.
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See also::
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include/dt-bindings/clock/qcom,gcc-msm8953.h
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include/dt-bindings/clock/qcom,gcc-mdm9607.h
2019
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allOf:
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required:
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- compatible
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- '#power-domain-cells'
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unevaluatedProperties: false
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