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Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-samsung' into clk-next
* clk-renesas: clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C clk: renesas: r8a779h0: Add Audio clocks clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP dt-bindings: clock: rcar-gen2: Remove obsolete header files dt-bindings: clock: r8a7779: Remove duplicate newline clk: renesas: Drop "Renesas" from individual driver descriptions clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments clk: renesas: r8a779h0: Add VIN clocks dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock clk: renesas: r8a77970: Use common cpg_lock clk: renesas: r8a779h0: Add CSI-2 clocks clk: renesas: r8a779h0: Add ISPCS clocks * clk-amlogic: clk: meson: add missing MODULE_DESCRIPTION() macros dt-bindings: clock: meson: a1: peripherals: support sys_pll input dt-bindings: clock: meson: a1: pll: introduce new syspll bindings clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL clk: meson: c3: add c3 clock peripherals controller driver clk: meson: c3: add support for the C3 SoC PLL clock dt-bindings: clock: add Amlogic C3 peripherals clock controller dt-bindings: clock: add Amlogic C3 SCMI clock controller support dt-bindings: clock: add Amlogic C3 PLL clock controller dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format clk: meson: s4: fix pwm_j_div parent clock clk: meson: s4: fix fixed_pll_dco clock * clk-allwinner: clk: sunxi-ng r40: Constify struct regmap_config clk: sunxi-ng: h616: Add clock/reset for GPADC dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks clk: sunxi: Remove unused struct 'gates_data' clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros * clk-samsung: clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical clk: samsung: Switch to use kmemdup_array() clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
5 parents 160d7b9 + e96b042 + d424c02 + 38bded8 + b1da66d commit bc060e6

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‎Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@ properties:
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- description: input fixed pll div7
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- description: input hifi pll
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- description: input oscillator (usually at 24MHz)
33+
- description: input sys pll
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minItems: 6 # sys_pll is optional
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clock-names:
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items:
@@ -39,6 +41,8 @@ properties:
3941
- const: fclk_div7
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- const: hifi_pll
4143
- const: xtal
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- const: sys_pll
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minItems: 6 # sys_pll is optional
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required:
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- compatible
@@ -65,9 +69,10 @@ examples:
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<&clkc_pll CLKID_FCLK_DIV5>,
6670
<&clkc_pll CLKID_FCLK_DIV7>,
6771
<&clkc_pll CLKID_HIFI_PLL>,
68-
<&xtal>;
72+
<&xtal>,
73+
<&clkc_pll CLKID_SYS_PLL>;
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clock-names = "fclk_div2", "fclk_div3",
7075
"fclk_div5", "fclk_div7",
71-
"hifi_pll", "xtal";
76+
"hifi_pll", "xtal", "sys_pll";
7277
};
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};

‎Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,11 +26,15 @@ properties:
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items:
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- description: input fixpll_in
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- description: input hifipll_in
29+
- description: input syspll_in
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minItems: 2 # syspll_in is optional
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clock-names:
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items:
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- const: fixpll_in
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- const: hifipll_in
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- const: syspll_in
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minItems: 2 # syspll_in is optional
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required:
3640
- compatible
@@ -53,7 +57,8 @@ examples:
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reg = <0 0x7c80 0 0x18c>;
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#clock-cells = <1>;
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clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
56-
<&clkc_periphs CLKID_HIFIPLL_IN>;
57-
clock-names = "fixpll_in", "hifipll_in";
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<&clkc_periphs CLKID_HIFIPLL_IN>,
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<&clkc_periphs CLKID_SYSPLL_IN>;
62+
clock-names = "fixpll_in", "hifipll_in", "syspll_in";
5863
};
5964
};

‎Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

Lines changed: 0 additions & 59 deletions
This file was deleted.

‎Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml

Lines changed: 201 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,201 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
3+
---
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$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic AXG Audio Clock Controller
8+
9+
maintainers:
10+
- Neil Armstrong <[email protected]>
11+
- Jerome Brunet <[email protected]>
12+
13+
description:
14+
The Amlogic AXG audio clock controller generates and supplies clock to the
15+
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
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devices.
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properties:
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compatible:
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enum:
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- amlogic,axg-audio-clkc
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- amlogic,g12a-audio-clkc
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- amlogic,sm1-audio-clkc
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: main peripheral bus clock
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- description: input plls to generate clock signals N0
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- description: input plls to generate clock signals N1
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- description: input plls to generate clock signals N2
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- description: input plls to generate clock signals N3
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- description: input plls to generate clock signals N4
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- description: input plls to generate clock signals N5
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- description: input plls to generate clock signals N6
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- description: input plls to generate clock signals N7
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- description: slave bit clock N0 provided by external components
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- description: slave bit clock N1 provided by external components
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- description: slave bit clock N2 provided by external components
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- description: slave bit clock N3 provided by external components
50+
- description: slave bit clock N4 provided by external components
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- description: slave bit clock N5 provided by external components
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- description: slave bit clock N6 provided by external components
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- description: slave bit clock N7 provided by external components
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- description: slave bit clock N8 provided by external components
55+
- description: slave bit clock N9 provided by external components
56+
- description: slave sample clock N0 provided by external components
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- description: slave sample clock N1 provided by external components
58+
- description: slave sample clock N2 provided by external components
59+
- description: slave sample clock N3 provided by external components
60+
- description: slave sample clock N4 provided by external components
61+
- description: slave sample clock N5 provided by external components
62+
- description: slave sample clock N6 provided by external components
63+
- description: slave sample clock N7 provided by external components
64+
- description: slave sample clock N8 provided by external components
65+
- description: slave sample clock N9 provided by external components
66+
67+
clock-names:
68+
minItems: 1
69+
items:
70+
- const: pclk
71+
- const: mst_in0
72+
- const: mst_in1
73+
- const: mst_in2
74+
- const: mst_in3
75+
- const: mst_in4
76+
- const: mst_in5
77+
- const: mst_in6
78+
- const: mst_in7
79+
- const: slv_sclk0
80+
- const: slv_sclk1
81+
- const: slv_sclk2
82+
- const: slv_sclk3
83+
- const: slv_sclk4
84+
- const: slv_sclk5
85+
- const: slv_sclk6
86+
- const: slv_sclk7
87+
- const: slv_sclk8
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- const: slv_sclk9
89+
- const: slv_lrclk0
90+
- const: slv_lrclk1
91+
- const: slv_lrclk2
92+
- const: slv_lrclk3
93+
- const: slv_lrclk4
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- const: slv_lrclk5
95+
- const: slv_lrclk6
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- const: slv_lrclk7
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- const: slv_lrclk8
98+
- const: slv_lrclk9
99+
100+
resets:
101+
description: internal reset line
102+
103+
required:
104+
- compatible
105+
- '#clock-cells'
106+
- reg
107+
- clocks
108+
- clock-names
109+
- resets
110+
111+
allOf:
112+
- if:
113+
properties:
114+
compatible:
115+
contains:
116+
enum:
117+
- amlogic,g12a-audio-clkc
118+
- amlogic,sm1-audio-clkc
119+
then:
120+
required:
121+
- '#reset-cells'
122+
else:
123+
properties:
124+
'#reset-cells': false
125+
126+
additionalProperties: false
127+
128+
examples:
129+
- |
130+
#include <dt-bindings/clock/axg-clkc.h>
131+
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
132+
apb {
133+
#address-cells = <2>;
134+
#size-cells = <2>;
135+
136+
clkc_audio: clock-controller@0 {
137+
compatible = "amlogic,axg-audio-clkc";
138+
reg = <0x0 0x0 0x0 0xb4>;
139+
#clock-cells = <1>;
140+
141+
clocks = <&clkc CLKID_AUDIO>,
142+
<&clkc CLKID_MPLL0>,
143+
<&clkc CLKID_MPLL1>,
144+
<&clkc CLKID_MPLL2>,
145+
<&clkc CLKID_MPLL3>,
146+
<&clkc CLKID_HIFI_PLL>,
147+
<&clkc CLKID_FCLK_DIV3>,
148+
<&clkc CLKID_FCLK_DIV4>,
149+
<&clkc CLKID_GP0_PLL>,
150+
<&slv_sclk0>,
151+
<&slv_sclk1>,
152+
<&slv_sclk2>,
153+
<&slv_sclk3>,
154+
<&slv_sclk4>,
155+
<&slv_sclk5>,
156+
<&slv_sclk6>,
157+
<&slv_sclk7>,
158+
<&slv_sclk8>,
159+
<&slv_sclk9>,
160+
<&slv_lrclk0>,
161+
<&slv_lrclk1>,
162+
<&slv_lrclk2>,
163+
<&slv_lrclk3>,
164+
<&slv_lrclk4>,
165+
<&slv_lrclk5>,
166+
<&slv_lrclk6>,
167+
<&slv_lrclk7>,
168+
<&slv_lrclk8>,
169+
<&slv_lrclk9>;
170+
clock-names = "pclk",
171+
"mst_in0",
172+
"mst_in1",
173+
"mst_in2",
174+
"mst_in3",
175+
"mst_in4",
176+
"mst_in5",
177+
"mst_in6",
178+
"mst_in7",
179+
"slv_sclk0",
180+
"slv_sclk1",
181+
"slv_sclk2",
182+
"slv_sclk3",
183+
"slv_sclk4",
184+
"slv_sclk5",
185+
"slv_sclk6",
186+
"slv_sclk7",
187+
"slv_sclk8",
188+
"slv_sclk9",
189+
"slv_lrclk0",
190+
"slv_lrclk1",
191+
"slv_lrclk2",
192+
"slv_lrclk3",
193+
"slv_lrclk4",
194+
"slv_lrclk5",
195+
"slv_lrclk6",
196+
"slv_lrclk7",
197+
"slv_lrclk8",
198+
"slv_lrclk9";
199+
resets = <&reset RESET_AUDIO>;
200+
};
201+
};

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