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204 | 204 | status = "disabled";
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205 | 205 | };
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206 | 206 |
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| 207 | + gmac: ethernet@10020000 { |
| 208 | + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; |
| 209 | + reg = <0x0 0x10020000 0x0 0x10000>; |
| 210 | + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, |
| 211 | + <&clkgen JH7100_CLK_GMAC_AHB>, |
| 212 | + <&clkgen JH7100_CLK_GMAC_PTP_REF>, |
| 213 | + <&clkgen JH7100_CLK_GMAC_TX_INV>, |
| 214 | + <&clkgen JH7100_CLK_GMAC_GTX>; |
| 215 | + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; |
| 216 | + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; |
| 217 | + reset-names = "ahb"; |
| 218 | + interrupts = <6>, <7>; |
| 219 | + interrupt-names = "macirq", "eth_wake_irq"; |
| 220 | + max-frame-size = <9000>; |
| 221 | + snps,multicast-filter-bins = <32>; |
| 222 | + snps,perfect-filter-entries = <128>; |
| 223 | + starfive,syscon = <&sysmain 0x70 0>; |
| 224 | + rx-fifo-depth = <32768>; |
| 225 | + tx-fifo-depth = <16384>; |
| 226 | + snps,axi-config = <&stmmac_axi_setup>; |
| 227 | + snps,fixed-burst; |
| 228 | + snps,force_thresh_dma_mode; |
| 229 | + status = "disabled"; |
| 230 | + |
| 231 | + stmmac_axi_setup: stmmac-axi-config { |
| 232 | + snps,wr_osr_lmt = <16>; |
| 233 | + snps,rd_osr_lmt = <16>; |
| 234 | + snps,blen = <256 128 64 32 0 0 0>; |
| 235 | + }; |
| 236 | + }; |
| 237 | + |
207 | 238 | clkgen: clock-controller@11800000 {
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208 | 239 | compatible = "starfive,jh7100-clkgen";
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209 | 240 | reg = <0x0 0x11800000 0x0 0x10000>;
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218 | 249 | #reset-cells = <1>;
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219 | 250 | };
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220 | 251 |
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| 252 | + sysmain: syscon@11850000 { |
| 253 | + compatible = "starfive,jh7100-sysmain", "syscon"; |
| 254 | + reg = <0x0 0x11850000 0x0 0x10000>; |
| 255 | + }; |
| 256 | + |
221 | 257 | i2c0: i2c@118b0000 {
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222 | 258 | compatible = "snps,designware-i2c";
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223 | 259 | reg = <0x0 0x118b0000 0x0 0x10000>;
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