riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro

During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.

Fixes: bee7fbc ("RISC-V CPU Idle Support")
Fixes: e7681be ("RISC-V: Split out the XIP fixups into their own file")

Signed-off-by: Frederik Haxel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

Author: fzi-haxel

arch/riscv/include/asm/xip_fixup.h

@@ -13,7 +13,7 @@
         add \reg, \reg, t0
 .endm
 .macro XIP_FIXUP_FLASH_OFFSET reg
-	la t1, __data_loc
+	la t0, __data_loc
 	REG_L t1, _xip_phys_offset
 	sub \reg, \reg, t1
 	add \reg, \reg, t0