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Ben Skeggs
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drm/nouveau/bo: use NVIDIA's headers for move move()
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
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-56
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5 files changed

+286
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‎drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,162 @@
1+
/*******************************************************************************
2+
Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3+
4+
Permission is hereby granted, free of charge, to any person obtaining a
5+
copy of this software and associated documentation files (the "Software"),
6+
to deal in the Software without restriction, including without limitation
7+
the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
and/or sell copies of the Software, and to permit persons to whom the
9+
Software is furnished to do so, subject to the following conditions:
10+
11+
The above copyright notice and this permission notice shall be included in
12+
all copies or substantial portions of the Software.
13+
14+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18+
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19+
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20+
DEALINGS IN THE SOFTWARE.
21+
22+
*******************************************************************************/
23+
24+
#ifndef _cla0b5_h_
25+
#define _cla0b5_h_
26+
27+
#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
28+
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
29+
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
30+
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
31+
#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
32+
#define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
33+
#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
34+
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
35+
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
36+
#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
37+
#define NVA0B5_LAUNCH_DMA (0x00000300)
38+
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
39+
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
40+
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
41+
#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
42+
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
43+
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000)
44+
#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
45+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
46+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000)
47+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
48+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002)
49+
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5
50+
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000)
51+
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001)
52+
#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002)
53+
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
54+
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
55+
#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
56+
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8
57+
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
58+
#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001)
59+
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9
60+
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
61+
#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001)
62+
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10
63+
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
64+
#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
65+
#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11
66+
#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000)
67+
#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001)
68+
#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12
69+
#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000)
70+
#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
71+
#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13
72+
#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)
73+
#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
74+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14
75+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000)
76+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001)
77+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002)
78+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003)
79+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004)
80+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005)
81+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006)
82+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007)
83+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A)
84+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B)
85+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C)
86+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D)
87+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E)
88+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18
89+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000)
90+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001)
91+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19
92+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000)
93+
#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001)
94+
#define NVA0B5_OFFSET_IN_UPPER (0x00000400)
95+
#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0
96+
#define NVA0B5_OFFSET_IN_LOWER (0x00000404)
97+
#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0
98+
#define NVA0B5_OFFSET_OUT_UPPER (0x00000408)
99+
#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0
100+
#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C)
101+
#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0
102+
#define NVA0B5_PITCH_IN (0x00000410)
103+
#define NVA0B5_PITCH_IN_VALUE 31:0
104+
#define NVA0B5_PITCH_OUT (0x00000414)
105+
#define NVA0B5_PITCH_OUT_VALUE 31:0
106+
#define NVA0B5_LINE_LENGTH_IN (0x00000418)
107+
#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0
108+
#define NVA0B5_LINE_COUNT (0x0000041C)
109+
#define NVA0B5_LINE_COUNT_VALUE 31:0
110+
#define NVA0B5_SET_REMAP_CONST_A (0x00000700)
111+
#define NVA0B5_SET_REMAP_CONST_A_V 31:0
112+
#define NVA0B5_SET_REMAP_CONST_B (0x00000704)
113+
#define NVA0B5_SET_REMAP_CONST_B_V 31:0
114+
#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708)
115+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0
116+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000)
117+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001)
118+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002)
119+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003)
120+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
121+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
122+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006)
123+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4
124+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000)
125+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001)
126+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002)
127+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003)
128+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004)
129+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005)
130+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006)
131+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8
132+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000)
133+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001)
134+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002)
135+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003)
136+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004)
137+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005)
138+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006)
139+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12
140+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000)
141+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001)
142+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002)
143+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003)
144+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004)
145+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005)
146+
#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006)
147+
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
148+
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
149+
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001)
150+
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002)
151+
#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003)
152+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20
153+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000)
154+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001)
155+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002)
156+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003)
157+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
158+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
159+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001)
160+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002)
161+
#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003)
162+
#endif // _cla0b5_h

‎drivers/gpu/drm/nouveau/nouveau_bo0039.c

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,9 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
4848
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
4949
{
5050
struct nvif_push *push = chan->chan.push;
51+
u32 src_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, old_reg);
5152
u32 src_offset = old_reg->start << PAGE_SHIFT;
53+
u32 dst_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, new_reg);
5254
u32 dst_offset = new_reg->start << PAGE_SHIFT;
5355
u32 page_count = new_reg->num_pages;
5456
int ret;
@@ -57,8 +59,8 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
5759
if (ret)
5860
return ret;
5961

60-
PUSH_NVSQ(push, NV039, 0x0184, nouveau_bo_mem_ctxdma(bo, chan, old_reg),
61-
0x0188, nouveau_bo_mem_ctxdma(bo, chan, new_reg));
62+
PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma,
63+
SET_CONTEXT_DMA_BUFFER_OUT, dst_ctxdma);
6264

6365
page_count = new_reg->num_pages;
6466
while (page_count) {
@@ -68,15 +70,20 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
6870
if (ret)
6971
return ret;
7072

71-
PUSH_NVSQ(push, NV039, 0x030c, src_offset,
72-
0x0310, dst_offset,
73-
0x0314, PAGE_SIZE, /* src_pitch */
74-
0x0318, PAGE_SIZE, /* dst_pitch */
75-
0x031c, PAGE_SIZE, /* line_length */
76-
0x0320, line_count,
77-
0x0324, 0x00000101,
78-
0x0328, 0x00000000);
79-
PUSH_NVSQ(push, NV039, 0x0100, 0x00000000);
73+
PUSH_MTHD(push, NV039, OFFSET_IN, src_offset,
74+
OFFSET_OUT, dst_offset,
75+
PITCH_IN, PAGE_SIZE,
76+
PITCH_OUT, PAGE_SIZE,
77+
LINE_LENGTH_IN, PAGE_SIZE,
78+
LINE_COUNT, line_count,
79+
80+
FORMAT,
81+
NVVAL(NV039, FORMAT, IN, 1) |
82+
NVVAL(NV039, FORMAT, OUT, 1),
83+
84+
BUFFER_NOTIFY, NV039_BUFFER_NOTIFY_WRITE_ONLY);
85+
86+
PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000);
8087

8188
page_count -= line_count;
8289
src_offset += (PAGE_SIZE * line_count);

‎drivers/gpu/drm/nouveau/nouveau_bo5039.c

Lines changed: 57 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -60,40 +60,70 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
6060
height = amount / stride;
6161

6262
if (src_tiled) {
63-
PUSH_NVSQ(push, NV5039, 0x0200, 0,
64-
0x0204, 0,
65-
0x0208, stride,
66-
0x020c, height,
67-
0x0210, 1,
68-
0x0214, 0,
69-
0x0218, 0);
63+
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
64+
NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, BLOCKLINEAR),
65+
66+
SET_SRC_BLOCK_SIZE,
67+
NVDEF(NV5039, SET_SRC_BLOCK_SIZE, WIDTH, ONE_GOB) |
68+
NVDEF(NV5039, SET_SRC_BLOCK_SIZE, HEIGHT, ONE_GOB) |
69+
NVDEF(NV5039, SET_SRC_BLOCK_SIZE, DEPTH, ONE_GOB),
70+
71+
SET_SRC_WIDTH, stride,
72+
SET_SRC_HEIGHT, height,
73+
SET_SRC_DEPTH, 1,
74+
SET_SRC_LAYER, 0,
75+
76+
SET_SRC_ORIGIN,
77+
NVVAL(NV5039, SET_SRC_ORIGIN, X, 0) |
78+
NVVAL(NV5039, SET_SRC_ORIGIN, Y, 0));
7079
} else {
71-
PUSH_NVSQ(push, NV5039, 0x0200, 1);
80+
PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT,
81+
NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, PITCH));
7282
}
7383

7484
if (dst_tiled) {
75-
PUSH_NVSQ(push, NV5039, 0x021c, 0,
76-
0x0220, 0,
77-
0x0224, stride,
78-
0x0228, height,
79-
0x022c, 1,
80-
0x0230, 0,
81-
0x0234, 0);
85+
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
86+
NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, BLOCKLINEAR),
87+
88+
SET_DST_BLOCK_SIZE,
89+
NVDEF(NV5039, SET_DST_BLOCK_SIZE, WIDTH, ONE_GOB) |
90+
NVDEF(NV5039, SET_DST_BLOCK_SIZE, HEIGHT, ONE_GOB) |
91+
NVDEF(NV5039, SET_DST_BLOCK_SIZE, DEPTH, ONE_GOB),
92+
93+
SET_DST_WIDTH, stride,
94+
SET_DST_HEIGHT, height,
95+
SET_DST_DEPTH, 1,
96+
SET_DST_LAYER, 0,
97+
98+
SET_DST_ORIGIN,
99+
NVVAL(NV5039, SET_DST_ORIGIN, X, 0) |
100+
NVVAL(NV5039, SET_DST_ORIGIN, Y, 0));
82101
} else {
83-
PUSH_NVSQ(push, NV5039, 0x021c, 1);
102+
PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT,
103+
NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, PITCH));
84104
}
85105

86-
PUSH_NVSQ(push, NV5039, 0x0238, upper_32_bits(src_offset),
87-
0x023c, upper_32_bits(dst_offset));
88-
PUSH_NVSQ(push, NV5039, 0x030c, lower_32_bits(src_offset),
89-
0x0310, lower_32_bits(dst_offset),
90-
0x0314, stride,
91-
0x0318, stride,
92-
0x031c, stride,
93-
0x0320, height,
94-
0x0324, 0x00000101,
95-
0x0328, 0x00000000);
96-
PUSH_NVSQ(push, NV5039, 0x0100, 0x00000000);
106+
PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER,
107+
NVVAL(NV5039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)),
108+
109+
OFFSET_OUT_UPPER,
110+
NVVAL(NV5039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)));
111+
112+
PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset),
113+
OFFSET_OUT, lower_32_bits(dst_offset),
114+
PITCH_IN, stride,
115+
PITCH_OUT, stride,
116+
LINE_LENGTH_IN, stride,
117+
LINE_COUNT, height,
118+
119+
FORMAT,
120+
NVDEF(NV5039, FORMAT, IN, ONE) |
121+
NVDEF(NV5039, FORMAT, OUT, ONE),
122+
123+
BUFFER_NOTIFY,
124+
NVDEF(NV5039, BUFFER_NOTIFY, TYPE, WRITE_ONLY));
125+
126+
PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000);
97127

98128
length -= amount;
99129
src_offset += amount;

‎drivers/gpu/drm/nouveau/nouveau_bo9039.c

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -53,15 +53,27 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
5353
if (ret)
5454
return ret;
5555

56-
PUSH_NVSQ(push, NV9039, 0x0238, upper_32_bits(dst_offset),
57-
0x023c, lower_32_bits(dst_offset));
58-
PUSH_NVSQ(push, NV9039, 0x030c, upper_32_bits(src_offset),
59-
0x0310, lower_32_bits(src_offset),
60-
0x0314, PAGE_SIZE, /* src_pitch */
61-
0x0318, PAGE_SIZE, /* dst_pitch */
62-
0x031c, PAGE_SIZE, /* line_length */
63-
0x0320, line_count);
64-
PUSH_NVSQ(push, NV9039, 0x0300, 0x00100110);
56+
PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER,
57+
NVVAL(NV9039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)),
58+
59+
OFFSET_OUT, lower_32_bits(dst_offset));
60+
61+
PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER,
62+
NVVAL(NV9039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)),
63+
64+
OFFSET_IN, lower_32_bits(src_offset),
65+
PITCH_IN, PAGE_SIZE,
66+
PITCH_OUT, PAGE_SIZE,
67+
LINE_LENGTH_IN, PAGE_SIZE,
68+
LINE_COUNT, line_count);
69+
70+
PUSH_MTHD(push, NV9039, LAUNCH_DMA,
71+
NVDEF(NV9039, LAUNCH_DMA, SRC_INLINE, FALSE) |
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NVDEF(NV9039, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
73+
NVDEF(NV9039, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
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NVDEF(NV9039, LAUNCH_DMA, COMPLETION_TYPE, FLUSH_DISABLE) |
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NVDEF(NV9039, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |
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NVDEF(NV9039, LAUNCH_DMA, SEMAPHORE_STRUCT_SIZE, ONE_WORD));
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6678
page_count -= line_count;
6779
src_offset += (PAGE_SIZE * line_count);

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