@@ -71,10 +71,12 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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#define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14)
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/* Shared receive buffer registers */
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#define KVASER_PCIEFD_SRB_BASE 0x1f200
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+ #define KVASER_PCIEFD_SRB_FIFO_LAST_REG (KVASER_PCIEFD_SRB_BASE + 0x1f4)
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#define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200)
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#define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204)
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#define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c)
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#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)
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+ #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214)
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#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)
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/* EPCS flash controller registers */
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#define KVASER_PCIEFD_SPI_BASE 0x1fc00
@@ -111,6 +113,9 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
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/* DMA support */
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#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
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+ /* SRB current packet level */
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+ #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff
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+
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/* DMA Enable */
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#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
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@@ -526,7 +531,7 @@ static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
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KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD |
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KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL |
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KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP |
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- KVASER_PCIEFD_KCAN_IRQ_TAR | KVASER_PCIEFD_KCAN_IRQ_TFD ;
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+ KVASER_PCIEFD_KCAN_IRQ_TAR ;
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iowrite32 (msk , can -> reg_base + KVASER_PCIEFD_KCAN_IEN_REG );
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@@ -554,6 +559,8 @@ static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
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if (can -> can .ctrlmode & CAN_CTRLMODE_LISTENONLY )
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mode |= KVASER_PCIEFD_KCAN_MODE_LOM ;
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+ else
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+ mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM ;
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mode |= KVASER_PCIEFD_KCAN_MODE_EEN ;
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mode |= KVASER_PCIEFD_KCAN_MODE_EPEN ;
@@ -572,7 +579,7 @@ static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can)
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spin_lock_irqsave (& can -> lock , irq );
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iowrite32 (-1 , can -> reg_base + KVASER_PCIEFD_KCAN_IRQ_REG );
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- iowrite32 (KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD ,
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+ iowrite32 (KVASER_PCIEFD_KCAN_IRQ_ABD ,
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can -> reg_base + KVASER_PCIEFD_KCAN_IEN_REG );
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status = ioread32 (can -> reg_base + KVASER_PCIEFD_KCAN_STAT_REG );
@@ -615,7 +622,7 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can)
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iowrite32 (0 , can -> reg_base + KVASER_PCIEFD_KCAN_IEN_REG );
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iowrite32 (-1 , can -> reg_base + KVASER_PCIEFD_KCAN_IRQ_REG );
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- iowrite32 (KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD ,
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+ iowrite32 (KVASER_PCIEFD_KCAN_IRQ_ABD ,
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can -> reg_base + KVASER_PCIEFD_KCAN_IEN_REG );
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mode = ioread32 (can -> reg_base + KVASER_PCIEFD_KCAN_MODE_REG );
@@ -719,6 +726,7 @@ static int kvaser_pciefd_stop(struct net_device *netdev)
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iowrite32 (0 , can -> reg_base + KVASER_PCIEFD_KCAN_IEN_REG );
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del_timer (& can -> bec_poll_timer );
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}
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+ can -> can .state = CAN_STATE_STOPPED ;
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close_candev (netdev );
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return ret ;
@@ -1007,8 +1015,7 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
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SET_NETDEV_DEV (netdev , & pcie -> pci -> dev );
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iowrite32 (-1 , can -> reg_base + KVASER_PCIEFD_KCAN_IRQ_REG );
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- iowrite32 (KVASER_PCIEFD_KCAN_IRQ_ABD |
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- KVASER_PCIEFD_KCAN_IRQ_TFD ,
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+ iowrite32 (KVASER_PCIEFD_KCAN_IRQ_ABD ,
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can -> reg_base + KVASER_PCIEFD_KCAN_IEN_REG );
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pcie -> can [i ] = can ;
@@ -1058,6 +1065,7 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
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{
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int i ;
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u32 srb_status ;
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+ u32 srb_packet_count ;
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dma_addr_t dma_addr [KVASER_PCIEFD_DMA_COUNT ];
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/* Disable the DMA */
@@ -1085,6 +1093,15 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
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KVASER_PCIEFD_SRB_CMD_RDB1 ,
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pcie -> reg_base + KVASER_PCIEFD_SRB_CMD_REG );
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+ /* Empty Rx FIFO */
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+ srb_packet_count = ioread32 (pcie -> reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG ) &
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+ KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK ;
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+ while (srb_packet_count ) {
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+ /* Drop current packet in FIFO */
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+ ioread32 (pcie -> reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG );
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+ srb_packet_count -- ;
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+ }
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+
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srb_status = ioread32 (pcie -> reg_base + KVASER_PCIEFD_SRB_STAT_REG );
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if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI )) {
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dev_err (& pcie -> pci -> dev , "DMA not idle before enabling\n" );
@@ -1425,9 +1442,6 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
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cmd = KVASER_PCIEFD_KCAN_CMD_AT ;
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cmd |= ++ can -> cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT ;
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iowrite32 (cmd , can -> reg_base + KVASER_PCIEFD_KCAN_CMD_REG );
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-
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- iowrite32 (KVASER_PCIEFD_KCAN_IRQ_TFD ,
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- can -> reg_base + KVASER_PCIEFD_KCAN_IEN_REG );
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} else if (p -> header [0 ] & KVASER_PCIEFD_SPACK_IDET &&
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p -> header [0 ] & KVASER_PCIEFD_SPACK_IRM &&
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cmdseq == (p -> header [1 ] & KVASER_PCIEFD_PACKET_SEQ_MSK ) &&
@@ -1714,15 +1728,6 @@ static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
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if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF )
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netdev_err (can -> can .dev , "Tx FIFO overflow\n" );
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- if (irq & KVASER_PCIEFD_KCAN_IRQ_TFD ) {
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- u8 count = ioread32 (can -> reg_base +
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- KVASER_PCIEFD_KCAN_TX_NPACKETS_REG ) & 0xff ;
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-
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- if (count == 0 )
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- iowrite32 (KVASER_PCIEFD_KCAN_CTRL_EFLUSH ,
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- can -> reg_base + KVASER_PCIEFD_KCAN_CTRL_REG );
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- }
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-
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if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP )
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netdev_err (can -> can .dev ,
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"Fail to change bittiming, when not in reset mode\n" );
@@ -1824,6 +1829,11 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev,
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if (err )
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goto err_teardown_can_ctrls ;
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+ err = request_irq (pcie -> pci -> irq , kvaser_pciefd_irq_handler ,
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+ IRQF_SHARED , KVASER_PCIEFD_DRV_NAME , pcie );
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+ if (err )
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+ goto err_teardown_can_ctrls ;
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+
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iowrite32 (KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 ,
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pcie -> reg_base + KVASER_PCIEFD_SRB_IRQ_REG );
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@@ -1844,18 +1854,15 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev,
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iowrite32 (KVASER_PCIEFD_SRB_CMD_RDB1 ,
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pcie -> reg_base + KVASER_PCIEFD_SRB_CMD_REG );
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- err = request_irq (pcie -> pci -> irq , kvaser_pciefd_irq_handler ,
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- IRQF_SHARED , KVASER_PCIEFD_DRV_NAME , pcie );
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- if (err )
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- goto err_teardown_can_ctrls ;
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-
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err = kvaser_pciefd_reg_candev (pcie );
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if (err )
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goto err_free_irq ;
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return 0 ;
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err_free_irq :
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+ /* Disable PCI interrupts */
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+ iowrite32 (0 , pcie -> reg_base + KVASER_PCIEFD_IEN_REG );
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free_irq (pcie -> pci -> irq , pcie );
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err_teardown_can_ctrls :
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