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Revert "parisc: Use ldcw instruction for SMP spinlock release barrier"
This reverts commit 9e5c602. No need to use the ldcw instruction as SMP spinlock release barrier. Revert it to gain back speed again. Signed-off-by: Helge Deller <[email protected]> Cc: <[email protected]> # v5.2+
1 parent 462fb75 commit 6e9f06e

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3 files changed

+24
-39
lines changed

3 files changed

+24
-39
lines changed

‎arch/parisc/include/asm/spinlock.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
3737
volatile unsigned int *a;
3838

3939
a = __ldcw_align(x);
40-
#ifdef CONFIG_SMP
41-
(void) __ldcw(a);
42-
#else
4340
mb();
44-
#endif
4541
*a = 1;
4642
}
4743

‎arch/parisc/kernel/entry.S

Lines changed: 20 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -454,9 +454,8 @@
454454
nop
455455
LDREG 0(\ptp),\pte
456456
bb,<,n \pte,_PAGE_PRESENT_BIT,3f
457-
LDCW 0(\tmp),\tmp1
458457
b \fault
459-
stw \spc,0(\tmp)
458+
stw,ma \spc,0(\tmp)
460459
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
461460
#endif
462461
2: LDREG 0(\ptp),\pte
@@ -465,22 +464,20 @@
465464
.endm
466465

467466
/* Release pa_tlb_lock lock without reloading lock address. */
468-
.macro tlb_unlock0 spc,tmp,tmp1
467+
.macro tlb_unlock0 spc,tmp
469468
#ifdef CONFIG_SMP
470469
98: or,COND(=) %r0,\spc,%r0
471-
LDCW 0(\tmp),\tmp1
472-
or,COND(=) %r0,\spc,%r0
473-
stw \spc,0(\tmp)
470+
stw,ma \spc,0(\tmp)
474471
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
475472
#endif
476473
.endm
477474

478475
/* Release pa_tlb_lock lock. */
479-
.macro tlb_unlock1 spc,tmp,tmp1
476+
.macro tlb_unlock1 spc,tmp
480477
#ifdef CONFIG_SMP
481478
98: load_pa_tlb_lock \tmp
482479
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
483-
tlb_unlock0 \spc,\tmp,\tmp1
480+
tlb_unlock0 \spc,\tmp
484481
#endif
485482
.endm
486483

@@ -1163,7 +1160,7 @@ dtlb_miss_20w:
11631160

11641161
idtlbt pte,prot
11651162

1166-
tlb_unlock1 spc,t0,t1
1163+
tlb_unlock1 spc,t0
11671164
rfir
11681165
nop
11691166

@@ -1189,7 +1186,7 @@ nadtlb_miss_20w:
11891186

11901187
idtlbt pte,prot
11911188

1192-
tlb_unlock1 spc,t0,t1
1189+
tlb_unlock1 spc,t0
11931190
rfir
11941191
nop
11951192

@@ -1223,7 +1220,7 @@ dtlb_miss_11:
12231220

12241221
mtsp t1, %sr1 /* Restore sr1 */
12251222

1226-
tlb_unlock1 spc,t0,t1
1223+
tlb_unlock1 spc,t0
12271224
rfir
12281225
nop
12291226

@@ -1256,7 +1253,7 @@ nadtlb_miss_11:
12561253

12571254
mtsp t1, %sr1 /* Restore sr1 */
12581255

1259-
tlb_unlock1 spc,t0,t1
1256+
tlb_unlock1 spc,t0
12601257
rfir
12611258
nop
12621259

@@ -1285,7 +1282,7 @@ dtlb_miss_20:
12851282

12861283
idtlbt pte,prot
12871284

1288-
tlb_unlock1 spc,t0,t1
1285+
tlb_unlock1 spc,t0
12891286
rfir
12901287
nop
12911288

@@ -1313,7 +1310,7 @@ nadtlb_miss_20:
13131310

13141311
idtlbt pte,prot
13151312

1316-
tlb_unlock1 spc,t0,t1
1313+
tlb_unlock1 spc,t0
13171314
rfir
13181315
nop
13191316

@@ -1420,7 +1417,7 @@ itlb_miss_20w:
14201417

14211418
iitlbt pte,prot
14221419

1423-
tlb_unlock1 spc,t0,t1
1420+
tlb_unlock1 spc,t0
14241421
rfir
14251422
nop
14261423

@@ -1444,7 +1441,7 @@ naitlb_miss_20w:
14441441

14451442
iitlbt pte,prot
14461443

1447-
tlb_unlock1 spc,t0,t1
1444+
tlb_unlock1 spc,t0
14481445
rfir
14491446
nop
14501447

@@ -1478,7 +1475,7 @@ itlb_miss_11:
14781475

14791476
mtsp t1, %sr1 /* Restore sr1 */
14801477

1481-
tlb_unlock1 spc,t0,t1
1478+
tlb_unlock1 spc,t0
14821479
rfir
14831480
nop
14841481

@@ -1502,7 +1499,7 @@ naitlb_miss_11:
15021499

15031500
mtsp t1, %sr1 /* Restore sr1 */
15041501

1505-
tlb_unlock1 spc,t0,t1
1502+
tlb_unlock1 spc,t0
15061503
rfir
15071504
nop
15081505

@@ -1532,7 +1529,7 @@ itlb_miss_20:
15321529

15331530
iitlbt pte,prot
15341531

1535-
tlb_unlock1 spc,t0,t1
1532+
tlb_unlock1 spc,t0
15361533
rfir
15371534
nop
15381535

@@ -1552,7 +1549,7 @@ naitlb_miss_20:
15521549

15531550
iitlbt pte,prot
15541551

1555-
tlb_unlock1 spc,t0,t1
1552+
tlb_unlock1 spc,t0
15561553
rfir
15571554
nop
15581555

@@ -1582,7 +1579,7 @@ dbit_trap_20w:
15821579

15831580
idtlbt pte,prot
15841581

1585-
tlb_unlock0 spc,t0,t1
1582+
tlb_unlock0 spc,t0
15861583
rfir
15871584
nop
15881585
#else
@@ -1608,7 +1605,7 @@ dbit_trap_11:
16081605

16091606
mtsp t1, %sr1 /* Restore sr1 */
16101607

1611-
tlb_unlock0 spc,t0,t1
1608+
tlb_unlock0 spc,t0
16121609
rfir
16131610
nop
16141611

@@ -1628,7 +1625,7 @@ dbit_trap_20:
16281625

16291626
idtlbt pte,prot
16301627

1631-
tlb_unlock0 spc,t0,t1
1628+
tlb_unlock0 spc,t0
16321629
rfir
16331630
nop
16341631
#endif

‎arch/parisc/kernel/syscall.S

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -640,9 +640,7 @@ cas_action:
640640
sub,<> %r28, %r25, %r0
641641
2: stw %r24, 0(%r26)
642642
/* Free lock */
643-
#ifdef CONFIG_SMP
644-
LDCW 0(%sr2,%r20), %r1 /* Barrier */
645-
#endif
643+
sync
646644
stw %r20, 0(%sr2,%r20)
647645
#if ENABLE_LWS_DEBUG
648646
/* Clear thread register indicator */
@@ -657,9 +655,7 @@ cas_action:
657655
3:
658656
/* Error occurred on load or store */
659657
/* Free lock */
660-
#ifdef CONFIG_SMP
661-
LDCW 0(%sr2,%r20), %r1 /* Barrier */
662-
#endif
658+
sync
663659
stw %r20, 0(%sr2,%r20)
664660
#if ENABLE_LWS_DEBUG
665661
stw %r0, 4(%sr2,%r20)
@@ -861,9 +857,7 @@ cas2_action:
861857

862858
cas2_end:
863859
/* Free lock */
864-
#ifdef CONFIG_SMP
865-
LDCW 0(%sr2,%r20), %r1 /* Barrier */
866-
#endif
860+
sync
867861
stw %r20, 0(%sr2,%r20)
868862
/* Enable interrupts */
869863
ssm PSW_SM_I, %r0
@@ -874,9 +868,7 @@ cas2_end:
874868
22:
875869
/* Error occurred on load or store */
876870
/* Free lock */
877-
#ifdef CONFIG_SMP
878-
LDCW 0(%sr2,%r20), %r1 /* Barrier */
879-
#endif
871+
sync
880872
stw %r20, 0(%sr2,%r20)
881873
ssm PSW_SM_I, %r0
882874
ldo 1(%r0),%r28

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