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Commit 6f9d713

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vinodkoulvinodkoul
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Merge branch 'fixes' into next
This brings rockchip,pcie3-phy changes into next which incoming patches are dependent on
2 parents 0338e1d + 47b3e2f commit 6f9d713

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6 files changed

+63
-31
lines changed

6 files changed

+63
-31
lines changed

‎drivers/phy/freescale/phy-fsl-imx8m-pcie.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy)
110110
/* Source clock from SoC internal PLL */
111111
writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
112112
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
113-
writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
114-
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
113+
if (imx8_phy->drvdata->variant != IMX8MM) {
114+
writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
115+
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
116+
}
115117
val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
116118
writel(val | ANA_AUX_RX_TERM_GND_EN,
117119
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);

‎drivers/phy/marvell/phy-mvebu-a3700-comphy.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -603,19 +603,20 @@ static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,
603603
u16 val;
604604

605605
fix_idx = 0;
606-
for (addr = 0; addr < 512; addr++) {
606+
for (addr = 0; addr < ARRAY_SIZE(gbe_phy_init); addr++) {
607607
/*
608608
* All PHY register values are defined in full for 3.125Gbps
609609
* SERDES speed. The values required for 1.25 Gbps are almost
610610
* the same and only few registers should be "fixed" in
611611
* comparison to 3.125 Gbps values. These register values are
612612
* stored in "gbe_phy_init_fix" array.
613613
*/
614-
if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) {
614+
if (!is_1gbps &&
615+
fix_idx < ARRAY_SIZE(gbe_phy_init_fix) &&
616+
gbe_phy_init_fix[fix_idx].addr == addr) {
615617
/* Use new value */
616618
val = gbe_phy_init_fix[fix_idx].value;
617-
if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix))
618-
fix_idx++;
619+
fix_idx++;
619620
} else {
620621
val = gbe_phy_init[addr];
621622
}

‎drivers/phy/qualcomm/phy-qcom-m31.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ static int m31usb_phy_probe(struct platform_device *pdev)
297297
return dev_err_probe(dev, PTR_ERR(qphy->phy),
298298
"failed to create phy\n");
299299

300-
qphy->vreg = devm_regulator_get(dev, "vdda-phy");
300+
qphy->vreg = devm_regulator_get(dev, "vdd");
301301
if (IS_ERR(qphy->vreg))
302302
return dev_err_probe(dev, PTR_ERR(qphy->vreg),
303303
"failed to get vreg\n");

‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@ enum qphy_reg_layout {
7777
QPHY_COM_BIAS_EN_CLKBUFLR_EN,
7878

7979
QPHY_DP_PHY_STATUS,
80+
QPHY_DP_PHY_VCO_DIV,
8081

8182
QPHY_TX_TX_POL_INV,
8283
QPHY_TX_TX_DRV_LVL,
@@ -102,6 +103,7 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
102103
[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,
103104

104105
[QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS,
106+
[QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV,
105107

106108
[QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV,
107109
[QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL,
@@ -126,6 +128,7 @@ static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
126128
[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,
127129

128130
[QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS,
131+
[QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV,
129132

130133
[QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV,
131134
[QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL,
@@ -2202,9 +2205,9 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
22022205
writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
22032206

22042207
if (reverse)
2205-
writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE);
2208+
writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
22062209
else
2207-
writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE);
2210+
writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
22082211

22092212
return reverse;
22102213
}
@@ -2214,6 +2217,7 @@ static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
22142217
const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
22152218
u32 phy_vco_div;
22162219
unsigned long pixel_freq;
2220+
const struct qmp_phy_cfg *cfg = qmp->cfg;
22172221

22182222
switch (dp_opts->link_rate) {
22192223
case 1620:
@@ -2236,7 +2240,7 @@ static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
22362240
/* Other link rates aren't supported */
22372241
return -EINVAL;
22382242
}
2239-
writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
2243+
writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);
22402244

22412245
clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
22422246
clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);

‎drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

Lines changed: 33 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -125,12 +125,15 @@ struct rockchip_combphy_grfcfg {
125125
};
126126

127127
struct rockchip_combphy_cfg {
128+
unsigned int num_phys;
129+
unsigned int phy_ids[3];
128130
const struct rockchip_combphy_grfcfg *grfcfg;
129131
int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
130132
};
131133

132134
struct rockchip_combphy_priv {
133135
u8 type;
136+
int id;
134137
void __iomem *mmio;
135138
int num_clks;
136139
struct clk_bulk_data *clks;
@@ -320,7 +323,7 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
320323
struct rockchip_combphy_priv *priv;
321324
const struct rockchip_combphy_cfg *phy_cfg;
322325
struct resource *res;
323-
int ret;
326+
int ret, id;
324327

325328
phy_cfg = of_device_get_match_data(dev);
326329
if (!phy_cfg) {
@@ -338,6 +341,15 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
338341
return ret;
339342
}
340343

344+
/* find the phy-id from the io address */
345+
priv->id = -ENODEV;
346+
for (id = 0; id < phy_cfg->num_phys; id++) {
347+
if (res->start == phy_cfg->phy_ids[id]) {
348+
priv->id = id;
349+
break;
350+
}
351+
}
352+
341353
priv->dev = dev;
342354
priv->type = PHY_NONE;
343355
priv->cfg = phy_cfg;
@@ -562,6 +574,12 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
562574
};
563575

564576
static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
577+
.num_phys = 3,
578+
.phy_ids = {
579+
0xfe820000,
580+
0xfe830000,
581+
0xfe840000,
582+
},
565583
.grfcfg = &rk3568_combphy_grfcfgs,
566584
.combphy_cfg = rk3568_combphy_cfg,
567585
};
@@ -578,8 +596,14 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
578596
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
579597
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
580598
rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
581-
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
582-
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
599+
switch (priv->id) {
600+
case 1:
601+
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
602+
break;
603+
case 2:
604+
rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
605+
break;
606+
}
583607
break;
584608
case PHY_TYPE_USB3:
585609
/* Set SSC downward spread spectrum */
@@ -736,6 +760,12 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
736760
};
737761

738762
static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
763+
.num_phys = 3,
764+
.phy_ids = {
765+
0xfee00000,
766+
0xfee10000,
767+
0xfee20000,
768+
},
739769
.grfcfg = &rk3588_combphy_grfcfgs,
740770
.combphy_cfg = rk3588_combphy_cfg,
741771
};

‎drivers/phy/rockchip/phy-rockchip-snps-pcie3.c

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@
4040
#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
4141
#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
4242
#define RK3588_LANE_AGGREGATION BIT(2)
43+
#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
44+
#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
4345

4446
struct rockchip_p3phy_ops;
4547

@@ -132,39 +134,32 @@ static const struct rockchip_p3phy_ops rk3568_ops = {
132134
static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
133135
{
134136
u32 reg = 0;
135-
u8 mode = 0;
137+
u8 mode = RK3588_LANE_AGGREGATION; /* default */
136138
int ret;
137139

138140
/* Deassert PCIe PMA output clamp mode */
139141
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
140142

141143
/* Set bifurcation if needed */
142144
for (int i = 0; i < priv->num_lanes; i++) {
143-
if (!priv->lanes[i])
144-
mode |= (BIT(i) << 3);
145-
146145
if (priv->lanes[i] > 1)
147-
mode |= (BIT(i) >> 1);
148-
}
149-
150-
if (!mode)
151-
reg = RK3588_LANE_AGGREGATION;
152-
else {
153-
if (mode & (BIT(0) | BIT(1)))
154-
reg |= RK3588_BIFURCATION_LANE_0_1;
155-
156-
if (mode & (BIT(2) | BIT(3)))
157-
reg |= RK3588_BIFURCATION_LANE_2_3;
146+
mode &= ~RK3588_LANE_AGGREGATION;
147+
if (priv->lanes[i] == 3)
148+
mode |= RK3588_BIFURCATION_LANE_0_1;
149+
if (priv->lanes[i] == 4)
150+
mode |= RK3588_BIFURCATION_LANE_2_3;
158151
}
159152

160-
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
153+
reg = mode;
154+
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
155+
RK3588_PCIE30_PHY_MODE_EN | reg);
161156

162157
/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
163158
if (!IS_ERR(priv->pipe_grf)) {
164-
reg = (mode & (BIT(6) | BIT(7))) >> 6;
159+
reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3);
165160
if (reg)
166161
regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
167-
(reg << 16) | reg);
162+
RK3588_PCIE1LN_SEL_EN | reg);
168163
}
169164

170165
reset_control_deassert(priv->p30phy);

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