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drm/msm/dpu: pull format flag definitions to mdp_format.h
In preparation to merger of formats databases, pull format flag definitions to mdp_format.h header, so that they are visibile to both dpu and mdp drivers. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/590425/ Link: https://lore.kernel.org/r/[email protected]
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-89
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9 files changed

+109
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‎drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c

Lines changed: 49 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,8 @@ bp, flg, fm, np) \
4444
.unpack_tight = 1, \
4545
.unpack_count = uc, \
4646
.bpp = bp, \
47-
.fetch_mode = fm, \
48-
.flags = flg, \
47+
.base.fetch_mode = fm, \
48+
.base.flags = flg, \
4949
.num_planes = np, \
5050
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
5151
}
@@ -63,8 +63,8 @@ alpha, bp, flg, fm, np, th) \
6363
.unpack_tight = 1, \
6464
.unpack_count = uc, \
6565
.bpp = bp, \
66-
.fetch_mode = fm, \
67-
.flags = flg, \
66+
.base.fetch_mode = fm, \
67+
.base.flags = flg, \
6868
.num_planes = np, \
6969
.tile_height = th \
7070
}
@@ -83,8 +83,8 @@ alpha, chroma, count, bp, flg, fm, np) \
8383
.unpack_tight = 1, \
8484
.unpack_count = count, \
8585
.bpp = bp, \
86-
.fetch_mode = fm, \
87-
.flags = flg, \
86+
.base.fetch_mode = fm, \
87+
.base.flags = flg, \
8888
.num_planes = np, \
8989
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
9090
}
@@ -101,8 +101,8 @@ alpha, chroma, count, bp, flg, fm, np) \
101101
.unpack_tight = 1, \
102102
.unpack_count = 2, \
103103
.bpp = 2, \
104-
.fetch_mode = fm, \
105-
.flags = flg, \
104+
.base.fetch_mode = fm, \
105+
.base.flags = flg, \
106106
.num_planes = np, \
107107
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
108108
}
@@ -120,8 +120,8 @@ flg, fm, np, th) \
120120
.unpack_tight = 1, \
121121
.unpack_count = 2, \
122122
.bpp = 2, \
123-
.fetch_mode = fm, \
124-
.flags = flg, \
123+
.base.fetch_mode = fm, \
124+
.base.flags = flg, \
125125
.num_planes = np, \
126126
.tile_height = th \
127127
}
@@ -138,8 +138,8 @@ flg, fm, np, th) \
138138
.unpack_tight = 0, \
139139
.unpack_count = 2, \
140140
.bpp = 2, \
141-
.fetch_mode = fm, \
142-
.flags = flg, \
141+
.base.fetch_mode = fm, \
142+
.base.flags = flg, \
143143
.num_planes = np, \
144144
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
145145
}
@@ -157,8 +157,8 @@ flg, fm, np, th) \
157157
.unpack_tight = 0, \
158158
.unpack_count = 2, \
159159
.bpp = 2, \
160-
.fetch_mode = fm, \
161-
.flags = flg, \
160+
.base.fetch_mode = fm, \
161+
.base.flags = flg, \
162162
.num_planes = np, \
163163
.tile_height = th \
164164
}
@@ -177,8 +177,8 @@ flg, fm, np) \
177177
.unpack_tight = 1, \
178178
.unpack_count = 1, \
179179
.bpp = bp, \
180-
.fetch_mode = fm, \
181-
.flags = flg, \
180+
.base.fetch_mode = fm, \
181+
.base.flags = flg, \
182182
.num_planes = np, \
183183
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
184184
}
@@ -365,115 +365,115 @@ static const struct dpu_format dpu_format_map[] = {
365365
INTERLEAVED_RGB_FMT(BGRA1010102,
366366
BPC8A, BPC8, BPC8, BPC8,
367367
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
368-
true, 4, DPU_FORMAT_FLAG_DX,
368+
true, 4, MSM_FORMAT_FLAG_DX,
369369
MDP_FETCH_LINEAR, 1),
370370

371371
INTERLEAVED_RGB_FMT(RGBA1010102,
372372
BPC8A, BPC8, BPC8, BPC8,
373373
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
374-
true, 4, DPU_FORMAT_FLAG_DX,
374+
true, 4, MSM_FORMAT_FLAG_DX,
375375
MDP_FETCH_LINEAR, 1),
376376

377377
INTERLEAVED_RGB_FMT(ABGR2101010,
378378
BPC8A, BPC8, BPC8, BPC8,
379379
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
380-
true, 4, DPU_FORMAT_FLAG_DX,
380+
true, 4, MSM_FORMAT_FLAG_DX,
381381
MDP_FETCH_LINEAR, 1),
382382

383383
INTERLEAVED_RGB_FMT(ARGB2101010,
384384
BPC8A, BPC8, BPC8, BPC8,
385385
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
386-
true, 4, DPU_FORMAT_FLAG_DX,
386+
true, 4, MSM_FORMAT_FLAG_DX,
387387
MDP_FETCH_LINEAR, 1),
388388

389389
INTERLEAVED_RGB_FMT(XRGB2101010,
390390
BPC8A, BPC8, BPC8, BPC8,
391391
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
392-
false, 4, DPU_FORMAT_FLAG_DX,
392+
false, 4, MSM_FORMAT_FLAG_DX,
393393
MDP_FETCH_LINEAR, 1),
394394

395395
INTERLEAVED_RGB_FMT(BGRX1010102,
396396
BPC8A, BPC8, BPC8, BPC8,
397397
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
398-
false, 4, DPU_FORMAT_FLAG_DX,
398+
false, 4, MSM_FORMAT_FLAG_DX,
399399
MDP_FETCH_LINEAR, 1),
400400

401401
INTERLEAVED_RGB_FMT(XBGR2101010,
402402
BPC8A, BPC8, BPC8, BPC8,
403403
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
404-
false, 4, DPU_FORMAT_FLAG_DX,
404+
false, 4, MSM_FORMAT_FLAG_DX,
405405
MDP_FETCH_LINEAR, 1),
406406

407407
INTERLEAVED_RGB_FMT(RGBX1010102,
408408
BPC8A, BPC8, BPC8, BPC8,
409409
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
410-
false, 4, DPU_FORMAT_FLAG_DX,
410+
false, 4, MSM_FORMAT_FLAG_DX,
411411
MDP_FETCH_LINEAR, 1),
412412

413413
PSEUDO_YUV_FMT(NV12,
414414
0, BPC8, BPC8, BPC8,
415415
C1_B_Cb, C2_R_Cr,
416-
CHROMA_420, DPU_FORMAT_FLAG_YUV,
416+
CHROMA_420, MSM_FORMAT_FLAG_YUV,
417417
MDP_FETCH_LINEAR, 2),
418418

419419
PSEUDO_YUV_FMT(NV21,
420420
0, BPC8, BPC8, BPC8,
421421
C2_R_Cr, C1_B_Cb,
422-
CHROMA_420, DPU_FORMAT_FLAG_YUV,
422+
CHROMA_420, MSM_FORMAT_FLAG_YUV,
423423
MDP_FETCH_LINEAR, 2),
424424

425425
PSEUDO_YUV_FMT(NV16,
426426
0, BPC8, BPC8, BPC8,
427427
C1_B_Cb, C2_R_Cr,
428-
CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
428+
CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
429429
MDP_FETCH_LINEAR, 2),
430430

431431
PSEUDO_YUV_FMT(NV61,
432432
0, BPC8, BPC8, BPC8,
433433
C2_R_Cr, C1_B_Cb,
434-
CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
434+
CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
435435
MDP_FETCH_LINEAR, 2),
436436

437437
PSEUDO_YUV_FMT_LOOSE(P010,
438438
0, BPC8, BPC8, BPC8,
439439
C1_B_Cb, C2_R_Cr,
440-
CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
440+
CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
441441
MDP_FETCH_LINEAR, 2),
442442

443443
INTERLEAVED_YUV_FMT(VYUY,
444444
0, BPC8, BPC8, BPC8,
445445
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
446-
false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
446+
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
447447
MDP_FETCH_LINEAR, 2),
448448

449449
INTERLEAVED_YUV_FMT(UYVY,
450450
0, BPC8, BPC8, BPC8,
451451
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
452-
false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
452+
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
453453
MDP_FETCH_LINEAR, 2),
454454

455455
INTERLEAVED_YUV_FMT(YUYV,
456456
0, BPC8, BPC8, BPC8,
457457
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
458-
false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
458+
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
459459
MDP_FETCH_LINEAR, 2),
460460

461461
INTERLEAVED_YUV_FMT(YVYU,
462462
0, BPC8, BPC8, BPC8,
463463
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
464-
false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
464+
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
465465
MDP_FETCH_LINEAR, 2),
466466

467467
PLANAR_YUV_FMT(YUV420,
468468
0, BPC8, BPC8, BPC8,
469469
C2_R_Cr, C1_B_Cb, C0_G_Y,
470-
false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
470+
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
471471
MDP_FETCH_LINEAR, 3),
472472

473473
PLANAR_YUV_FMT(YVU420,
474474
0, BPC8, BPC8, BPC8,
475475
C1_B_Cb, C2_R_Cr, C0_G_Y,
476-
false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
476+
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
477477
MDP_FETCH_LINEAR, 3),
478478
};
479479

@@ -487,13 +487,13 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
487487
INTERLEAVED_RGB_FMT_TILED(BGR565,
488488
0, BPC5, BPC6, BPC5,
489489
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
490-
false, 2, DPU_FORMAT_FLAG_COMPRESSED,
490+
false, 2, MSM_FORMAT_FLAG_COMPRESSED,
491491
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
492492

493493
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
494494
BPC8A, BPC8, BPC8, BPC8,
495495
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
496-
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
496+
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
497497
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
498498

499499
/* ARGB8888 and ABGR8888 purposely have the same color
@@ -503,37 +503,37 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
503503
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
504504
BPC8A, BPC8, BPC8, BPC8,
505505
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
506-
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
506+
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
507507
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
508508

509509
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
510510
BPC8A, BPC8, BPC8, BPC8,
511511
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
512-
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
512+
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
513513
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
514514

515515
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
516516
BPC8A, BPC8, BPC8, BPC8,
517517
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
518-
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
518+
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
519519
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
520520

521521
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
522522
BPC8A, BPC8, BPC8, BPC8,
523523
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
524-
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
524+
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
525525
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
526526

527527
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
528528
BPC8A, BPC8, BPC8, BPC8,
529529
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
530-
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
530+
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
531531
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
532532

533533
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
534534
BPC8A, BPC8, BPC8, BPC8,
535535
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
536-
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
536+
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
537537
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
538538

539539
/* XRGB2101010 and ARGB2101010 purposely have the same color
@@ -543,22 +543,22 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
543543
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
544544
BPC8A, BPC8, BPC8, BPC8,
545545
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
546-
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
546+
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
547547
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
548548

549549
PSEUDO_YUV_FMT_TILED(NV12,
550550
0, BPC8, BPC8, BPC8,
551551
C1_B_Cb, C2_R_Cr,
552-
CHROMA_420, DPU_FORMAT_FLAG_YUV |
553-
DPU_FORMAT_FLAG_COMPRESSED,
552+
CHROMA_420, MSM_FORMAT_FLAG_YUV |
553+
MSM_FORMAT_FLAG_COMPRESSED,
554554
MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
555555

556556
PSEUDO_YUV_FMT_TILED(P010,
557557
0, BPC8, BPC8, BPC8,
558558
C1_B_Cb, C2_R_Cr,
559-
CHROMA_420, DPU_FORMAT_FLAG_DX |
560-
DPU_FORMAT_FLAG_YUV |
561-
DPU_FORMAT_FLAG_COMPRESSED,
559+
CHROMA_420, MSM_FORMAT_FLAG_DX |
560+
MSM_FORMAT_FLAG_YUV |
561+
MSM_FORMAT_FLAG_COMPRESSED,
562562
MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
563563
};
564564

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h

Lines changed: 7 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@
99
#include <linux/err.h>
1010

1111
#include "msm_drv.h"
12-
#include "mdp_common.xml.h"
12+
13+
#include "disp/mdp_format.h"
1314

1415
#define DPU_DBG_NAME "dpu"
1516

@@ -36,25 +37,11 @@
3637
#define DPU_MAX_DE_CURVES 3
3738
#endif
3839

39-
enum dpu_format_flags {
40-
DPU_FORMAT_FLAG_YUV_BIT,
41-
DPU_FORMAT_FLAG_DX_BIT,
42-
DPU_FORMAT_FLAG_COMPRESSED_BIT,
43-
};
44-
45-
#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
46-
#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
47-
#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
48-
49-
#define DPU_FORMAT_IS_YUV(X) ((X)->flags & DPU_FORMAT_FLAG_YUV)
50-
#define DPU_FORMAT_IS_DX(X) ((X)->flags & DPU_FORMAT_FLAG_DX)
51-
#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
52-
#define DPU_FORMAT_IS_TILE(X) \
53-
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
54-
!((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
55-
#define DPU_FORMAT_IS_UBWC(X) \
56-
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
57-
((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
40+
#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
41+
#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
42+
#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
43+
#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
44+
#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
5845

5946
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
6047
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
@@ -331,8 +318,6 @@ enum dpu_3d_blend_mode {
331318
* @bpp: bytes per pixel
332319
* @alpha_enable: whether the format has an alpha channel
333320
* @num_planes: number of planes (including meta data planes)
334-
* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
335-
* @flags: usage bit flags
336321
* @tile_width: format tile width
337322
* @tile_height: format tile height
338323
*/
@@ -348,8 +333,6 @@ struct dpu_format {
348333
u8 bpp;
349334
u8 alpha_enable;
350335
u8 num_planes;
351-
enum mdp_fetch_mode fetch_mode;
352-
unsigned long flags;
353336
u16 tile_width;
354337
u16 tile_height;
355338
};

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -267,10 +267,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
267267
(fmt->unpack_align_msb << 18) |
268268
((fmt->bpp - 1) << 9);
269269

270-
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
270+
if (!DPU_FORMAT_IS_LINEAR(fmt)) {
271271
if (DPU_FORMAT_IS_UBWC(fmt))
272272
opmode |= MDSS_MDP_OP_BWC_EN;
273-
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
273+
src_format |= (fmt->base.fetch_mode & 3) << 30; /*FRAME_FORMAT */
274274
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
275275
DPU_FETCH_CONFIG_RESET_VALUE |
276276
ctx->ubwc->highest_bank_bit << 18);

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