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bebarinobebarino
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Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'clk-imx' into clk-next
* clk-hisi: clk: hi6220: use CLK_OF_DECLARE_DRIVER * clk-amlogic: clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code clk: meson: axg_audio: add sm1 support clk: meson: axg-audio: provide clk top signal name clk: meson: axg-audio: prepare sm1 addition clk: meson: axg-audio: fix regmap last register clk: meson: axg-audio: remove useless defines dt-bindings: clock: meson: add sm1 resets to the axg-audio controller dt-bindings: clk: axg-audio: add sm1 bindings clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes clk: meson: g12a: fix cpu clock rate setting clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate * clk-samsung: clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume clk: samsung: exynos5420: Add VPLL rate table clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU clk: samsung: exynos5433: Fix error paths * clk-renesas: (23 commits) clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960 dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support clk: renesas: r8a77965: Remove superfluous semicolon dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate() clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate() clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() clk: renesas: r8a774b1: Add TMU clock clk: renesas: cpg-mssr: Add r8a774b1 support dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate() clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() clk: renesas: rcar-gen3: Improve arithmetic divisions clk: renesas: rcar-gen2: Improve arithmetic divisions clk: renesas: Remove R-Car Gen2 legacy DT clock support ... * clk-imx: clk: imx: imx8mq: fix sys3_pll_out_sels clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code clk: imx7ulp: Correct DDR clock mux options clk: imx7ulp: Correct system clock source option #7 clk: imx: imx8mq: mark sys1/2_pll as fixed clock clk: imx: imx8mn: mark sys_pll1/2 as fixed clock clk: imx: imx8mm: mark sys_pll1/2 as fixed clock clk: imx8mn: Define gates for pll1/2 fixed dividers clk: imx8mm: Define gates for pll1/2 fixed dividers clk: imx8mq: Define gates for pll1/2 fixed dividers clk: imx: clk-pll14xx: Make two variables static clk: imx8mq: Add VIDEO2_PLL clock clk: imx8mn: Use common 1443X/1416X PLL clock structure clk: imx8mm: Move 1443X/1416X PLL clock structure to common place clk: imx: pll14xx: Fix quick switch of S/K parameter
6 parents 1303231 + f1edb49 + fac3810 + 6063244 + b7c1b40 + bfd582a commit 74ca928

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-1601
lines changed

‎Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,8 @@ devices.
77
Required Properties:
88

99
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
10-
"amlogic,g12a-audio-clkc" for G12A.
10+
"amlogic,g12a-audio-clkc" for G12A,
11+
"amlogic,sm1-audio-clkc" for S905X3.
1112
- reg : physical base address of the clock controller and length of
1213
memory mapped region.
1314
- clocks : a list of phandle + clock-specifier pairs for the clocks listed

‎Documentation/devicetree/bindings/clock/imx7ulp-clock.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 {
8282
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
8383
<&scg1 IMX7ULP_CLK_UPLL>,
8484
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
85-
<&scg1 IMX7ULP_CLK_MIPI_PLL>,
8685
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
8786
<&scg1 IMX7ULP_CLK_ROSC>,
8887
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

‎Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -19,14 +19,16 @@ Required Properties:
1919
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
2020
- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
2121
- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
22+
- "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)
2223
- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
2324
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
2425
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
2526
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
2627
- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
2728
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
2829
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
29-
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
30+
- "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)
31+
- "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)
3032
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
3133
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
3234
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
@@ -40,10 +42,11 @@ Required Properties:
4042
clock-names
4143
- clock-names: List of external parent clock names. Valid names are:
4244
- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
43-
r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
44-
r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
45-
r8a77995)
46-
- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
45+
r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
46+
r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,
47+
r8a77980, r8a77990, r8a77995)
48+
- "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,
49+
r8a77970, r8a77980)
4750
- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
4851
r8a7793, r8a7794)
4952

‎Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

Lines changed: 0 additions & 60 deletions
This file was deleted.

‎Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ Required properties:
4646
Example (R-Car H3):
4747

4848
usb2_clksel: clock-controller@e6590630 {
49-
compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
49+
compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
5050
"renesas,rcar-gen3-usb2-clock-sel";
5151
reg = <0 0xe6590630 0 0x02>;
5252
clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;

‎drivers/clk/hisilicon/clk-hi6220.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,8 @@ static void __init hi6220_clk_ao_init(struct device_node *np)
8686
hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
8787
ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
8888
}
89-
CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
89+
/* Allow reset driver to probe as well */
90+
CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
9091

9192

9293
/* clocks in sysctrl */

‎drivers/clk/imx/clk-imx6sll.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -107,12 +107,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
107107

108108
hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
109109

110-
hws[IMX6SLL_CLK_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
111-
hws[IMX6SLL_CLK_OSC] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
110+
hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
111+
hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
112112

113113
/* ipp_di clock is external input */
114-
hws[IMX6SLL_CLK_IPP_DI0] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di0"));
115-
hws[IMX6SLL_CLK_IPP_DI1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di1"));
114+
hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
115+
hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
116116

117117
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
118118
base = of_iomap(np, 0);

‎drivers/clk/imx/clk-imx6sx.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -139,16 +139,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
139139

140140
hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
141141

142-
hws[IMX6SX_CLK_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
143-
hws[IMX6SX_CLK_OSC] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
142+
hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
143+
hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
144144

145145
/* ipp_di clock is external input */
146-
hws[IMX6SX_CLK_IPP_DI0] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di0"));
147-
hws[IMX6SX_CLK_IPP_DI1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di1"));
146+
hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
147+
hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
148148

149149
/* Clock source from external clock via CLK1/2 PAD */
150-
hws[IMX6SX_CLK_ANACLK1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "anaclk1"));
151-
hws[IMX6SX_CLK_ANACLK2] = __clk_get_hw(of_clk_get_by_name(ccm_node, "anaclk2"));
150+
hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1");
151+
hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2");
152152

153153
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
154154
base = of_iomap(np, 0);

‎drivers/clk/imx/clk-imx6ul.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -126,12 +126,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
126126

127127
hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
128128

129-
hws[IMX6UL_CLK_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
130-
hws[IMX6UL_CLK_OSC] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
129+
hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
130+
hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
131131

132132
/* ipp_di clock is external input */
133-
hws[IMX6UL_CLK_IPP_DI0] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di0"));
134-
hws[IMX6UL_CLK_IPP_DI1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di1"));
133+
hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
134+
hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
135135

136136
np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");
137137
base = of_iomap(np, 0);

‎drivers/clk/imx/clk-imx7d.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -403,8 +403,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
403403
hws = clk_hw_data->hws;
404404

405405
hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
406-
hws[IMX7D_OSC_24M_CLK] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
407-
hws[IMX7D_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
406+
hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
407+
hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
408408

409409
np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
410410
base = of_iomap(np, 0);

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