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Merge tag 'imx-fixes-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 6.0, 2nd round: - A couple of TQMa8MPQL device tree fixes from Alexander Stein on button GPIOs and PCF85063 RTC alarm pinctrl. - Include phy-imx8-pcie.h header in tqma8mqml-mba8mx device tree to fix build errors when this SoM dtsi is included on customer carrier boards. - Remove GPU power domain reset from i.MX8MN device tree to fix a sporadical hang seen with GPUMIX powering up. - Correct CPLD_Dn GPIO label mapping for Toradex Verdin based Menlo board. - Add ARCH_NXP back to defconfig, which was dropped accidentally by commit 566e373 ("arm64: Kconfig.platforms: Group NXP platforms together"). - Add missing #reset-cells for i.MX8ULP PCC clock controllers. - Update PMIC voltages for imx8mm-verdin board to fix an issue with one Toradex SKU that uses a consumer-grade chip that is capable of going up to 1.8GHz at 1.00V. - A series of imx8mp-venice-gw74xx device tree changes from Tim Harvey to fix things on CAN STBY polarity, KSZ9477 CPU uplink port and phy-mode. * tag 'imx-fixes-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mp-venice-gw74xx: fix port/phy validation arm64: dts: imx8mp-venice-gw74xx: fix ksz9477 cpu port arm64: dts: imx8mp-venice-gw74xx: fix CAN STBY polarity arm64: dts: tqma8mqml: Include phy-imx8-pcie.h header arm64: defconfig: enable ARCH_NXP arm64: dts: imx8mp-tqma8mpql-mba8mpxl: add missing pinctrl for RTC alarm arm64: dts: imx8mm-verdin: extend pmic voltages arm64: dts: imx8ulp: add #reset-cells for pcc arm64: dts: tqma8mpxl-ba8mpxl: Fix button GPIOs arm64: dts: imx8mn: remove GPU power domain reset arm64: dts: imx8mm: Reverse CPLD_Dn GPIO label mapping on MX8Menlo Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 96c9b51 + f7fc391 commit 7b9a516

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‎arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -152,11 +152,11 @@
152152
* CPLD_reset is RESET_SOFT in schematic
153153
*/
154154
gpio-line-names =
155-
"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
156-
"", "CPLD_D[0]", "", "",
157-
"", "", "", "CPLD_D[2]",
158-
"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
159-
"CPLD_D[7]", "", "", "",
155+
"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
156+
"", "CPLD_D[7]", "", "",
157+
"", "", "", "CPLD_D[5]",
158+
"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
159+
"CPLD_D[0]", "", "", "",
160160
"", "", "", "",
161161
"", "", "", "KBD_intK",
162162
"", "", "", "";

‎arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@
55

66
/dts-v1/;
77

8-
#include <dt-bindings/phy/phy-imx8-pcie.h>
98
#include "imx8mm-tqma8mqml.dtsi"
109
#include "mba8mx.dtsi"
1110

‎arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
* Copyright 2020-2021 TQ-Systems GmbH
44
*/
55

6+
#include <dt-bindings/phy/phy-imx8-pcie.h>
67
#include "imx8mm.dtsi"
78

89
/ {

‎arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -367,17 +367,17 @@
367367
nxp,dvs-standby-voltage = <850000>;
368368
regulator-always-on;
369369
regulator-boot-on;
370-
regulator-max-microvolt = <950000>;
371-
regulator-min-microvolt = <850000>;
370+
regulator-max-microvolt = <1050000>;
371+
regulator-min-microvolt = <805000>;
372372
regulator-name = "On-module +VDD_ARM (BUCK2)";
373373
regulator-ramp-delay = <3125>;
374374
};
375375

376376
reg_vdd_dram: BUCK3 {
377377
regulator-always-on;
378378
regulator-boot-on;
379-
regulator-max-microvolt = <950000>;
380-
regulator-min-microvolt = <850000>;
379+
regulator-max-microvolt = <1000000>;
380+
regulator-min-microvolt = <805000>;
381381
regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
382382
};
383383

@@ -416,7 +416,7 @@
416416
reg_vdd_snvs: LDO2 {
417417
regulator-always-on;
418418
regulator-boot-on;
419-
regulator-max-microvolt = <900000>;
419+
regulator-max-microvolt = <800000>;
420420
regulator-min-microvolt = <800000>;
421421
regulator-name = "On-module +V0.8_SNVS (LDO2)";
422422
};

‎arch/arm64/boot/dts/freescale/imx8mn.dtsi

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -672,7 +672,6 @@
672672
<&clk IMX8MN_CLK_GPU_SHADER>,
673673
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
674674
<&clk IMX8MN_CLK_GPU_AHB>;
675-
resets = <&src IMX8MQ_RESET_GPU_RESET>;
676675
};
677676

678677
pgc_dispmix: power-domain@3 {

‎arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,13 +57,13 @@
5757
switch-1 {
5858
label = "S12";
5959
linux,code = <BTN_0>;
60-
gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
60+
gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
6161
};
6262

6363
switch-2 {
6464
label = "S13";
6565
linux,code = <BTN_1>;
66-
gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
66+
gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
6767
};
6868
};
6969

@@ -394,6 +394,8 @@
394394

395395
&pcf85063 {
396396
/* RTC_EVENT# is connected on MBa8MPxL */
397+
pinctrl-names = "default";
398+
pinctrl-0 = <&pinctrl_pcf85063>;
397399
interrupt-parent = <&gpio4>;
398400
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
399401
};
@@ -630,6 +632,10 @@
630632
fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */
631633
};
632634

635+
pinctrl_pcf85063: pcf85063grp {
636+
fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>;
637+
};
638+
633639
/* LVDS Backlight */
634640
pinctrl_pwm2: pwm2grp {
635641
fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>;

‎arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -123,8 +123,7 @@
123123
pinctrl-names = "default";
124124
pinctrl-0 = <&pinctrl_reg_can>;
125125
regulator-name = "can2_stby";
126-
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
127-
enable-active-high;
126+
gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
128127
regulator-min-microvolt = <3300000>;
129128
regulator-max-microvolt = <3300000>;
130129
};
@@ -484,35 +483,40 @@
484483
lan1: port@0 {
485484
reg = <0>;
486485
label = "lan1";
486+
phy-mode = "internal";
487487
local-mac-address = [00 00 00 00 00 00];
488488
};
489489

490490
lan2: port@1 {
491491
reg = <1>;
492492
label = "lan2";
493+
phy-mode = "internal";
493494
local-mac-address = [00 00 00 00 00 00];
494495
};
495496

496497
lan3: port@2 {
497498
reg = <2>;
498499
label = "lan3";
500+
phy-mode = "internal";
499501
local-mac-address = [00 00 00 00 00 00];
500502
};
501503

502504
lan4: port@3 {
503505
reg = <3>;
504506
label = "lan4";
507+
phy-mode = "internal";
505508
local-mac-address = [00 00 00 00 00 00];
506509
};
507510

508511
lan5: port@4 {
509512
reg = <4>;
510513
label = "lan5";
514+
phy-mode = "internal";
511515
local-mac-address = [00 00 00 00 00 00];
512516
};
513517

514-
port@6 {
515-
reg = <6>;
518+
port@5 {
519+
reg = <5>;
516520
label = "cpu";
517521
ethernet = <&fec>;
518522
phy-mode = "rgmii-id";

‎arch/arm64/boot/dts/freescale/imx8ulp.dtsi

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,7 @@
172172
compatible = "fsl,imx8ulp-pcc3";
173173
reg = <0x292d0000 0x10000>;
174174
#clock-cells = <1>;
175+
#reset-cells = <1>;
175176
};
176177

177178
tpm5: tpm@29340000 {
@@ -270,6 +271,7 @@
270271
compatible = "fsl,imx8ulp-pcc4";
271272
reg = <0x29800000 0x10000>;
272273
#clock-cells = <1>;
274+
#reset-cells = <1>;
273275
};
274276

275277
lpi2c6: i2c@29840000 {
@@ -414,6 +416,7 @@
414416
compatible = "fsl,imx8ulp-pcc5";
415417
reg = <0x2da70000 0x10000>;
416418
#clock-cells = <1>;
419+
#reset-cells = <1>;
417420
};
418421
};
419422

‎arch/arm64/configs/defconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ CONFIG_ARCH_KEEMBAY=y
4848
CONFIG_ARCH_MEDIATEK=y
4949
CONFIG_ARCH_MESON=y
5050
CONFIG_ARCH_MVEBU=y
51+
CONFIG_ARCH_NXP=y
5152
CONFIG_ARCH_MXC=y
5253
CONFIG_ARCH_NPCM=y
5354
CONFIG_ARCH_QCOM=y

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