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Evan Quanalexdeucher
Evan Quan
authored and
alexdeucher
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drm/amd/powerplay: move ppfeature mask setting to smu_cmn.c
Considering they are shared by all ASICs. And we are moving to centralize all feature enablement/support checking and setting APIs in smu_cmn.c. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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-142
lines changed

10 files changed

+190
-142
lines changed

‎drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

Lines changed: 2 additions & 135 deletions
Original file line numberDiff line numberDiff line change
@@ -59,147 +59,33 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
5959
return __smu_message_names[type];
6060
}
6161

62-
#undef __SMU_DUMMY_MAP
63-
#define __SMU_DUMMY_MAP(fea) #fea
64-
static const char* __smu_feature_names[] = {
65-
SMU_FEATURE_MASKS
66-
};
67-
68-
const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
69-
{
70-
if (feature < 0 || feature >= SMU_FEATURE_COUNT)
71-
return "unknown smu feature";
72-
return __smu_feature_names[feature];
73-
}
74-
7562
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
7663
{
7764
size_t size = 0;
78-
int ret = 0, i = 0;
79-
uint32_t feature_mask[2] = { 0 };
80-
int32_t feature_index = 0;
81-
uint32_t count = 0;
82-
uint32_t sort_feature[SMU_FEATURE_COUNT];
83-
uint64_t hw_feature_count = 0;
8465

8566
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
8667
return -EOPNOTSUPP;
8768

8869
mutex_lock(&smu->mutex);
8970

90-
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
91-
if (ret)
92-
goto failed;
71+
size = smu_get_pp_feature_mask(smu, buf);
9372

94-
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
95-
feature_mask[1], feature_mask[0]);
96-
97-
for (i = 0; i < SMU_FEATURE_COUNT; i++) {
98-
feature_index = smu_cmn_to_asic_specific_index(smu,
99-
CMN2ASIC_MAPPING_FEATURE,
100-
i);
101-
if (feature_index < 0)
102-
continue;
103-
sort_feature[feature_index] = i;
104-
hw_feature_count++;
105-
}
106-
107-
for (i = 0; i < hw_feature_count; i++) {
108-
size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
109-
count++,
110-
smu_get_feature_name(smu, sort_feature[i]),
111-
i,
112-
!!smu_feature_is_enabled(smu, sort_feature[i]) ?
113-
"enabled" : "disabled");
114-
}
115-
116-
failed:
11773
mutex_unlock(&smu->mutex);
11874

11975
return size;
12076
}
12177

122-
static int smu_feature_update_enable_state(struct smu_context *smu,
123-
uint64_t feature_mask,
124-
bool enabled)
125-
{
126-
struct smu_feature *feature = &smu->smu_feature;
127-
int ret = 0;
128-
129-
if (enabled) {
130-
ret = smu_send_smc_msg_with_param(smu,
131-
SMU_MSG_EnableSmuFeaturesLow,
132-
lower_32_bits(feature_mask),
133-
NULL);
134-
if (ret)
135-
return ret;
136-
ret = smu_send_smc_msg_with_param(smu,
137-
SMU_MSG_EnableSmuFeaturesHigh,
138-
upper_32_bits(feature_mask),
139-
NULL);
140-
if (ret)
141-
return ret;
142-
} else {
143-
ret = smu_send_smc_msg_with_param(smu,
144-
SMU_MSG_DisableSmuFeaturesLow,
145-
lower_32_bits(feature_mask),
146-
NULL);
147-
if (ret)
148-
return ret;
149-
ret = smu_send_smc_msg_with_param(smu,
150-
SMU_MSG_DisableSmuFeaturesHigh,
151-
upper_32_bits(feature_mask),
152-
NULL);
153-
if (ret)
154-
return ret;
155-
}
156-
157-
mutex_lock(&feature->mutex);
158-
if (enabled)
159-
bitmap_or(feature->enabled, feature->enabled,
160-
(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
161-
else
162-
bitmap_andnot(feature->enabled, feature->enabled,
163-
(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
164-
mutex_unlock(&feature->mutex);
165-
166-
return ret;
167-
}
168-
16978
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
17079
{
17180
int ret = 0;
172-
uint32_t feature_mask[2] = { 0 };
173-
uint64_t feature_2_enabled = 0;
174-
uint64_t feature_2_disabled = 0;
175-
uint64_t feature_enables = 0;
17681

17782
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
17883
return -EOPNOTSUPP;
17984

18085
mutex_lock(&smu->mutex);
18186

182-
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
183-
if (ret)
184-
goto out;
185-
186-
feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
187-
188-
feature_2_enabled = ~feature_enables & new_mask;
189-
feature_2_disabled = feature_enables & ~new_mask;
190-
191-
if (feature_2_enabled) {
192-
ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
193-
if (ret)
194-
goto out;
195-
}
196-
if (feature_2_disabled) {
197-
ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
198-
if (ret)
199-
goto out;
200-
}
87+
ret = smu_set_pp_feature_mask(smu, new_mask);
20188

202-
out:
20389
mutex_unlock(&smu->mutex);
20490

20591
return ret;
@@ -540,25 +426,6 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
540426
return ret;
541427
}
542428

543-
int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
544-
bool enable)
545-
{
546-
struct smu_feature *feature = &smu->smu_feature;
547-
int feature_id;
548-
549-
feature_id = smu_cmn_to_asic_specific_index(smu,
550-
CMN2ASIC_MAPPING_FEATURE,
551-
mask);
552-
if (feature_id < 0)
553-
return -EINVAL;
554-
555-
WARN_ON(feature_id > feature->feature_num);
556-
557-
return smu_feature_update_enable_state(smu,
558-
1ULL << feature_id,
559-
enable);
560-
}
561-
562429
static int smu_set_funcs(struct amdgpu_device *adev)
563430
{
564431
struct smu_context *smu = &adev->smu;

‎drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1838,7 +1838,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
18381838

18391839
if (enable) {
18401840
if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1841-
ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1841+
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
18421842
if (ret) {
18431843
dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
18441844
return ret;
@@ -1847,7 +1847,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
18471847
power_gate->vcn_gated = false;
18481848
} else {
18491849
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1850-
ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1850+
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
18511851
if (ret) {
18521852
dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
18531853
return ret;
@@ -2312,6 +2312,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
23122312
.set_df_cstate = arcturus_set_df_cstate,
23132313
.allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
23142314
.log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2315+
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2316+
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
23152317
};
23162318

23172319
void arcturus_set_ppt_funcs(struct smu_context *smu)

‎drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -584,6 +584,8 @@ struct pptable_funcs {
584584
int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
585585
int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
586586
void (*log_thermal_throttling_event)(struct smu_context *smu);
587+
size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
588+
int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
587589
};
588590

589591
typedef enum {
@@ -729,9 +731,6 @@ extern const struct amd_ip_funcs smu_ip_funcs;
729731
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
730732
extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
731733

732-
extern int smu_feature_set_enabled(struct smu_context *smu,
733-
enum smu_feature_mask mask, bool enable);
734-
735734
int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
736735
void *table_data, bool drv2smu);
737736

@@ -771,7 +770,6 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count);
771770
int smu_set_ac_dc(struct smu_context *smu);
772771
bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
773772
const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
774-
const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
775773
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
776774
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
777775
int smu_force_clk_levels(struct smu_context *smu,

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2329,6 +2329,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
23292329
.run_btc = navi10_run_btc,
23302330
.disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
23312331
.set_power_source = smu_v11_0_set_power_source,
2332+
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2333+
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
23322334
};
23332335

23342336
void navi10_set_ppt_funcs(struct smu_context *smu)

‎drivers/gpu/drm/amd/powerplay/renoir_ppt.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1025,6 +1025,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
10251025
.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
10261026
.set_driver_table_location = smu_v12_0_set_driver_table_location,
10271027
.is_dpm_running = renoir_is_dpm_running,
1028+
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1029+
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
10281030
};
10291031

10301032
void renoir_set_ppt_funcs(struct smu_context *smu)

‎drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2477,6 +2477,8 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
24772477
.mode1_reset = smu_v11_0_mode1_reset,
24782478
.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
24792479
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2480+
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2481+
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
24802482
};
24812483

24822484
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)

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