Skip to content

Commit 8034945

Browse files
vsyrjalavsyrjala
committed
drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
Add consistent definitions for the per-lane PHY TX registers on bxt/glk. The current situation is a slight mess with some registers having a LN0 define, while others have a parametrized per-lane definition. v2: Adjust gvt accordingly Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
1 parent 8221a62 commit 8034945

File tree

5 files changed

+35
-35
lines changed

5 files changed

+35
-35
lines changed

‎drivers/gpu/drm/i915/display/intel_dpio_phy.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -294,13 +294,13 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
294294
val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
295295
intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
296296

297-
val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
297+
val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, 0));
298298
val &= ~(MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK);
299299
val |= MARGIN_000(trans->entries[level].bxt.margin) |
300300
UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale);
301301
intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
302302

303-
val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
303+
val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, 0));
304304
val &= ~SCALE_DCOMP_METHOD;
305305
if (trans->entries[level].bxt.enable)
306306
val |= SCALE_DCOMP_METHOD;
@@ -311,7 +311,7 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
311311

312312
intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
313313

314-
val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
314+
val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, 0));
315315
val &= ~DE_EMPHASIS_MASK;
316316
val |= DE_EMPHASIS(trans->entries[level].bxt.deemphasis);
317317
intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);

‎drivers/gpu/drm/i915/display/intel_dpll_mgr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2117,7 +2117,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
21172117
drm_err(&i915->drm, "PLL %d not locked\n", port);
21182118

21192119
if (IS_GEMINILAKE(i915)) {
2120-
temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN0(phy, ch));
2120+
temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
21212121
temp |= DCC_DELAY_RANGE_2;
21222122
intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
21232123
}

‎drivers/gpu/drm/i915/gvt/handlers.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2763,15 +2763,15 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
27632763

27642764
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
27652765
NULL, bxt_pcs_dw12_grp_write);
2766-
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
2766+
MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
27672767
bxt_port_tx_dw3_read, NULL);
27682768
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
27692769
NULL, bxt_pcs_dw12_grp_write);
2770-
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
2770+
MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
27712771
bxt_port_tx_dw3_read, NULL);
27722772
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
27732773
NULL, bxt_pcs_dw12_grp_write);
2774-
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
2774+
MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
27752775
bxt_port_tx_dw3_read, NULL);
27762776
MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
27772777
MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -555,6 +555,10 @@
555555
(reg_ch1) - _BXT_PHY0_BASE))
556556
#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
557557
_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
558+
#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
559+
((lane) & 1) * 0x80)
560+
#define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \
561+
_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
558562

559563
#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
560564
#define MIPIO_RST_CTRL (1 << 2)
@@ -747,18 +751,15 @@
747751
_PORT_PCS_DW12_GRP_C)
748752

749753
/* BXT PHY TX registers */
750-
#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
751-
((lane) & 1) * 0x80)
752-
753754
#define _PORT_TX_DW2_LN0_A 0x162508
754755
#define _PORT_TX_DW2_LN0_B 0x6C508
755756
#define _PORT_TX_DW2_LN0_C 0x6C908
756757
#define _PORT_TX_DW2_GRP_A 0x162D08
757758
#define _PORT_TX_DW2_GRP_B 0x6CD08
758759
#define _PORT_TX_DW2_GRP_C 0x6CF08
759-
#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
760-
_PORT_TX_DW2_LN0_B, \
761-
_PORT_TX_DW2_LN0_C)
760+
#define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
761+
_PORT_TX_DW2_LN0_B, \
762+
_PORT_TX_DW2_LN0_C)
762763
#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
763764
_PORT_TX_DW2_GRP_B, \
764765
_PORT_TX_DW2_GRP_C)
@@ -773,9 +774,9 @@
773774
#define _PORT_TX_DW3_GRP_A 0x162D0C
774775
#define _PORT_TX_DW3_GRP_B 0x6CD0C
775776
#define _PORT_TX_DW3_GRP_C 0x6CF0C
776-
#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
777-
_PORT_TX_DW3_LN0_B, \
778-
_PORT_TX_DW3_LN0_C)
777+
#define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
778+
_PORT_TX_DW3_LN0_B, \
779+
_PORT_TX_DW3_LN0_C)
779780
#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
780781
_PORT_TX_DW3_GRP_B, \
781782
_PORT_TX_DW3_GRP_C)
@@ -788,9 +789,9 @@
788789
#define _PORT_TX_DW4_GRP_A 0x162D10
789790
#define _PORT_TX_DW4_GRP_B 0x6CD10
790791
#define _PORT_TX_DW4_GRP_C 0x6CF10
791-
#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
792-
_PORT_TX_DW4_LN0_B, \
793-
_PORT_TX_DW4_LN0_C)
792+
#define BXT_PORT_TX_DW4_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
793+
_PORT_TX_DW4_LN0_B, \
794+
_PORT_TX_DW4_LN0_C)
794795
#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
795796
_PORT_TX_DW4_GRP_B, \
796797
_PORT_TX_DW4_GRP_C)
@@ -803,9 +804,9 @@
803804
#define _PORT_TX_DW5_GRP_A 0x162D14
804805
#define _PORT_TX_DW5_GRP_B 0x6CD14
805806
#define _PORT_TX_DW5_GRP_C 0x6CF14
806-
#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
807-
_PORT_TX_DW5_LN0_B, \
808-
_PORT_TX_DW5_LN0_C)
807+
#define BXT_PORT_TX_DW5_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
808+
_PORT_TX_DW5_LN0_B, \
809+
_PORT_TX_DW5_LN0_C)
809810
#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
810811
_PORT_TX_DW5_GRP_B, \
811812
_PORT_TX_DW5_GRP_C)
@@ -816,10 +817,9 @@
816817
#define _PORT_TX_DW14_LN0_B 0x6C538
817818
#define _PORT_TX_DW14_LN0_C 0x6C938
818819
#define LATENCY_OPTIM REG_BIT(30)
819-
#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
820-
_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
821-
_PORT_TX_DW14_LN0_C) + \
822-
_BXT_LANE_OFFSET(lane))
820+
#define BXT_PORT_TX_DW14_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
821+
_PORT_TX_DW14_LN0_B, \
822+
_PORT_TX_DW14_LN0_C)
823823

824824
/* UAIMI scratch pad register 1 */
825825
#define UAIMI_SPR1 _MMIO(0x4F074)

‎drivers/gpu/drm/i915/intel_gvt_mmio_table.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,11 +1155,11 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
11551155
MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0));
11561156
MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0));
11571157
MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0));
1158-
MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0));
1158+
MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY0, DPIO_CH0, 0));
11591159
MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0));
1160-
MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0));
1160+
MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0));
11611161
MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0));
1162-
MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0));
1162+
MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY0, DPIO_CH0, 0));
11631163
MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0));
11641164
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0));
11651165
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1));
@@ -1180,11 +1180,11 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
11801180
MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1));
11811181
MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1));
11821182
MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1));
1183-
MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1));
1183+
MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY0, DPIO_CH1, 0));
11841184
MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1));
1185-
MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1));
1185+
MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0));
11861186
MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1));
1187-
MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1));
1187+
MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY0, DPIO_CH1, 0));
11881188
MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1));
11891189
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0));
11901190
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1));
@@ -1205,11 +1205,11 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
12051205
MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0));
12061206
MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0));
12071207
MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0));
1208-
MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0));
1208+
MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY1, DPIO_CH0, 0));
12091209
MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0));
1210-
MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0));
1210+
MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0));
12111211
MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0));
1212-
MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0));
1212+
MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY1, DPIO_CH0, 0));
12131213
MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0));
12141214
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0));
12151215
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1));

0 commit comments

Comments
 (0)