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153 | 153 | #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
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154 | 154 | #define MTK_DP_ENC0_P0_3094 0x3094
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155 | 155 | #define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0)
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156 |
| -#define MTK_DP_ENC0_P0_30A0 0x30a0 |
157 |
| -#define DP_ENC0_30A0_MASK (BIT(7) | BIT(8) | BIT(12)) |
158 | 156 | #define MTK_DP_ENC0_P0_30A4 0x30a4
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159 | 157 | #define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0)
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160 | 158 | #define MTK_DP_ENC0_P0_30A8 0x30a8
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171 | 169 | #define MTK_DP_ENC0_P0_312C 0x312c
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172 | 170 | #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)
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173 | 171 | #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
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174 |
| -#define MTK_DP_ENC0_P0_3130 0x3130 |
175 |
| -#define MTK_DP_ENC0_P0_3138 0x3138 |
176 | 172 | #define MTK_DP_ENC0_P0_3154 0x3154
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177 | 173 | #define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0)
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178 | 174 | #define MTK_DP_ENC0_P0_3158 0x3158
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206 | 202 | #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0)
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207 | 203 | #define SDP_PACKET_W_DP_ENC1_P0 BIT(5)
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208 | 204 | #define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5)
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209 |
| -#define MTK_DP_ENC1_P0_328C 0x328c |
210 |
| -#define VSC_DATA_RDY_VESA_DP_ENC1_P0_MASK BIT(7) |
211 | 205 | #define MTK_DP_ENC1_P0_3300 0x3300
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212 | 206 | #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL 2
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213 | 207 | #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)
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