Skip to content

Commit 8d741ec

Browse files
bebarinobebarino
committed
Merge branches 'clk-imx', 'clk-ux500' and 'clk-debugfs' into clk-next
* clk-imx: (21 commits) clk: imx: Make CLK_IMX8ULP select MXC_CLK clk: imx: imx6ul: Fix csi clk gate register clk: imx: imx6ul: Move csi_sel mux to correct base register clk: imx: Fix the build break when clk-imx8ulp build as module clk: imx: Add the pcc reset controller support on imx8ulp clk: imx: Add clock driver for imx8ulp clk: imx: Update the pfdv2 for 8ulp specific support clk: imx: disable the pfd when set pfdv2 clock rate clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulp clk: imx: disable i.mx7ulp composite clock during initialization clk: imx: Update the compsite driver to support imx8ulp clk: imx: Update the pllv4 to support imx8ulp dt-bindings: clock: Add imx8ulp clock support clk: imx: Rework imx_clk_hw_pll14xx wrapper clk: imx: Rework all imx_clk_hw_composite wrappers clk: imx: Rework all clk_hw_register_divider wrappers clk: imx: Rework all clk_hw_register_mux wrappers clk: imx: Rework all clk_hw_register_gate2 wrappers clk: imx: Rework all clk_hw_register_gate wrappers clk: imx: Make mux/mux2 clk based helpers use clk_hw based ones ... * clk-ux500: clk: ux500: Add driver for the reset portions of PRCC dt-bindings: clock: u8500: Rewrite in YAML and extend * clk-debugfs: clk: use clk_core_get_rate_recalc() in clk_rate_get()
4 parents b43e2d5 + 897a54f + b14cbdf + dd742ca commit 8d741ec

24 files changed

+1696
-426
lines changed

‎Documentation/devicetree/bindings/clock/imx8ulp-cgc-clock.yaml

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: NXP i.MX8ULP Clock Generation & Control(CGC) Module Binding
8+
9+
maintainers:
10+
- Jacky Bai <[email protected]>
11+
12+
description: |
13+
On i.MX8ULP, The clock sources generation, distribution and management is
14+
under the control of several CGCs & PCCs modules. The CGC modules generate
15+
and distribute clocks on the device.
16+
17+
properties:
18+
compatible:
19+
enum:
20+
- fsl,imx8ulp-cgc1
21+
- fsl,imx8ulp-cgc2
22+
23+
reg:
24+
maxItems: 1
25+
26+
'#clock-cells':
27+
const: 1
28+
29+
required:
30+
- compatible
31+
- reg
32+
- '#clock-cells'
33+
34+
additionalProperties: false
35+
36+
examples:
37+
# Clock Generation & Control Module node:
38+
- |
39+
clock-controller@292c0000 {
40+
compatible = "fsl,imx8ulp-cgc1";
41+
reg = <0x292c0000 0x10000>;
42+
#clock-cells = <1>;
43+
};

‎Documentation/devicetree/bindings/clock/imx8ulp-pcc-clock.yaml

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding
8+
9+
maintainers:
10+
- Jacky Bai <[email protected]>
11+
12+
description: |
13+
On i.MX8ULP, The clock sources generation, distribution and management is
14+
under the control of several CGCs & PCCs modules. The PCC modules control
15+
software reset, clock selection, optional division and clock gating mode
16+
for peripherals.
17+
18+
properties:
19+
compatible:
20+
enum:
21+
- fsl,imx8ulp-pcc3
22+
- fsl,imx8ulp-pcc4
23+
- fsl,imx8ulp-pcc5
24+
25+
reg:
26+
maxItems: 1
27+
28+
'#clock-cells':
29+
const: 1
30+
31+
'#reset-cells':
32+
const: 1
33+
34+
required:
35+
- compatible
36+
- reg
37+
- '#clock-cells'
38+
- '#reset-cells'
39+
40+
additionalProperties: false
41+
42+
examples:
43+
# Peripheral Clock Control Module node:
44+
- |
45+
clock-controller@292d0000 {
46+
compatible = "fsl,imx8ulp-pcc3";
47+
reg = <0x292d0000 0x10000>;
48+
#clock-cells = <1>;
49+
#reset-cells = <1>;
50+
};

‎Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml

Lines changed: 121 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,121 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: ST-Ericsson DB8500 (U8500) clocks
8+
9+
maintainers:
10+
- Ulf Hansson <[email protected]>
11+
- Linus Walleij <[email protected]>
12+
13+
description: While named "U8500 clocks" these clocks are inside the
14+
DB8500 digital baseband system-on-chip and its siblings such as
15+
DB8520. These bindings consider the clocks present in the SoC
16+
itself, not off-chip clocks. There are four different on-chip
17+
clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
18+
control management unit) clocks and PRCC (peripheral reset and
19+
clock controller) clocks. For some reason PRCC 4 does not exist so
20+
the itemization can be a bit unintuitive.
21+
22+
properties:
23+
compatible:
24+
enum:
25+
- stericsson,u8500-clks
26+
- stericsson,u8540-clks
27+
- stericsson,u9540-clks
28+
29+
reg:
30+
items:
31+
- description: PRCC 1 register area
32+
- description: PRCC 2 register area
33+
- description: PRCC 3 register area
34+
- description: PRCC 5 register area
35+
- description: PRCC 6 register area
36+
37+
prcmu-clock:
38+
description: A subnode with one clock cell for PRCMU (power, reset, control
39+
management unit) clocks. The cell indicates which PRCMU clock in the
40+
prcmu-clock node the consumer wants to use.
41+
type: object
42+
43+
properties:
44+
'#clock-cells':
45+
const: 1
46+
47+
additionalProperties: false
48+
49+
prcc-periph-clock:
50+
description: A subnode with two clock cells for PRCC (peripheral
51+
reset and clock controller) peripheral clocks. The first cell indicates
52+
which PRCC block the consumer wants to use, possible values are 1, 2, 3,
53+
5, 6. The second cell indicates which clock inside the PRCC block it
54+
wants, possible values are 0 thru 31.
55+
type: object
56+
57+
properties:
58+
'#clock-cells':
59+
const: 2
60+
61+
additionalProperties: false
62+
63+
prcc-kernel-clock:
64+
description: A subnode with two clock cells for PRCC (peripheral reset
65+
and clock controller) kernel clocks. The first cell indicates which PRCC
66+
block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The
67+
second cell indicates which clock inside the PRCC block it wants, possible
68+
values are 0 thru 31.
69+
type: object
70+
71+
properties:
72+
'#clock-cells':
73+
const: 2
74+
75+
additionalProperties: false
76+
77+
prcc-reset-controller:
78+
description: A subnode with two reset cells for the reset portions of the
79+
PRCC (peripheral reset and clock controller). The first cell indicates
80+
which PRCC block the consumer wants to use, possible values are 1, 2, 3
81+
5 and 6. The second cell indicates which reset line inside the PRCC block
82+
it wants to control, possible values are 0 thru 31.
83+
type: object
84+
85+
properties:
86+
'#reset-cells':
87+
const: 2
88+
89+
additionalProperties: false
90+
91+
rtc32k-clock:
92+
description: A subnode with zero clock cells for the 32kHz RTC clock.
93+
type: object
94+
95+
properties:
96+
'#clock-cells':
97+
const: 0
98+
99+
additionalProperties: false
100+
101+
smp-twd-clock:
102+
description: A subnode for the ARM SMP Timer Watchdog cluster with zero
103+
clock cells.
104+
type: object
105+
106+
properties:
107+
'#clock-cells':
108+
const: 0
109+
110+
additionalProperties: false
111+
112+
required:
113+
- compatible
114+
- reg
115+
- prcmu-clock
116+
- prcc-periph-clock
117+
- prcc-kernel-clock
118+
- rtc32k-clock
119+
- smp-twd-clock
120+
121+
additionalProperties: false

‎Documentation/devicetree/bindings/clock/ux500.txt

Lines changed: 0 additions & 64 deletions
This file was deleted.

‎arch/arm/mach-ux500/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ menuconfig ARCH_U8500
2929
select REGULATOR_DB8500_PRCMU
3030
select REGULATOR_FIXED_VOLTAGE
3131
select SOC_BUS
32+
select RESET_CONTROLLER
3233
help
3334
Support for ST-Ericsson's Ux500 architecture
3435

‎drivers/clk/clk.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3108,7 +3108,10 @@ static int clk_rate_get(void *data, u64 *val)
31083108
{
31093109
struct clk_core *core = data;
31103110

3111-
*val = core->rate;
3111+
clk_prepare_lock();
3112+
*val = clk_core_get_rate_recalc(core);
3113+
clk_prepare_unlock();
3114+
31123115
return 0;
31133116
}
31143117

‎drivers/clk/imx/Kconfig

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,3 +98,10 @@ config CLK_IMX8QXP
9898
select MXC_CLK_SCU
9999
help
100100
Build the driver for IMX8QXP SCU based clocks.
101+
102+
config CLK_IMX8ULP
103+
tristate "IMX8ULP CCM Clock Driver"
104+
depends on ARCH_MXC || COMPILE_TEST
105+
select MXC_CLK
106+
help
107+
Build the driver for i.MX8ULP CCM Clock Driver

‎drivers/clk/imx/Makefile

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,8 @@ clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
3131
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
3232
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
3333

34+
obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o
35+
3436
obj-$(CONFIG_CLK_IMX1) += clk-imx1.o
3537
obj-$(CONFIG_CLK_IMX25) += clk-imx25.o
3638
obj-$(CONFIG_CLK_IMX27) += clk-imx27.o

0 commit comments

Comments
 (0)