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Merge branches 'clk-leak', 'clk-rockchip', 'clk-renesas' and 'clk-at91' into clk-next
- Clock power management for new SAMA7G5 SoC - Updates to the master clock driver and sam9x60-pll to be able to use cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while changing the frequency via DVFS - Power management refinement with the use of save_context()/restore_context() on each clock driver to specify their use in case of Backup mode only * clk-leak: clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling paths * clk-rockchip: clk: rockchip: use module_platform_driver_probe clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L} clk: rockchip: rk3399: make CPU clocks critical * clk-renesas: clk: renesas: r8a779[56]x: Add MLP clocks clk: renesas: r9a07g044: Add SDHI clock and reset entries clk: renesas: rzg2l: Add SDHI clk mux support clk: renesas: r8a779a0: Add RPC support clk: renesas: cpg-lib: Move RPC clock registration to the library clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller clk: renesas: r8a779a0: Add Z0 and Z1 clock support clk: renesas: r9a07g044: Add GbEthernet clock/reset clk: renesas: rzg2l: Add support to handle coupled clocks clk: renesas: r9a07g044: Add ethernet clock sources clk: renesas: rzg2l: Add support to handle MUX clocks clk: renesas: r8a779a0: Add TPU clock clk: renesas: rzg2l: Fix clk status function clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical * clk-at91: clk: at91: sama7g5: set low limit for mck0 at 32KHz clk: at91: sama7g5: remove prescaler part of master clock clk: at91: clk-master: add notifier for divider clk: at91: clk-sam9x60-pll: add notifier for div part of PLL clk: at91: clk-master: fix prescaler logic clk: at91: clk-master: mask mckr against layout->mask clk: at91: clk-master: check if div or pres is zero clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL clk: at91: pmc: add sama7g5 to the list of available pmcs clk: at91: clk-master: improve readability by using local variables clk: at91: clk-master: add register definition for sama7g5's master clock clk: at91: sama7g5: add securam's peripheral clock clk: at91: pmc: execute suspend/resume only for backup mode clk: at91: re-factor clocks suspend/resume clk: at91: check pmc node status before registering syscore ops
5 parents a379e16 + af9617b + 8d27b14 + bada038 + 0b59e61 commit b43e2d5

37 files changed

+1543
-412
lines changed

drivers/clk/at91/at91rm9200.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
152152
"masterck_pres",
153153
&at91rm9200_master_layout,
154154
&rm9200_mck_characteristics,
155-
&rm9200_mck_lock, CLK_SET_RATE_GATE);
155+
&rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
156156
if (IS_ERR(hw))
157157
goto err_free;
158158

drivers/clk/at91/at91sam9260.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
429429
&at91rm9200_master_layout,
430430
data->mck_characteristics,
431431
&at91sam9260_mck_lock,
432-
CLK_SET_RATE_GATE);
432+
CLK_SET_RATE_GATE, 0);
433433
if (IS_ERR(hw))
434434
goto err_free;
435435

drivers/clk/at91/at91sam9g45.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
164164
&at91rm9200_master_layout,
165165
&mck_characteristics,
166166
&at91sam9g45_mck_lock,
167-
CLK_SET_RATE_GATE);
167+
CLK_SET_RATE_GATE, 0);
168168
if (IS_ERR(hw))
169169
goto err_free;
170170

drivers/clk/at91/at91sam9n12.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
191191
&at91sam9x5_master_layout,
192192
&mck_characteristics,
193193
&at91sam9n12_mck_lock,
194-
CLK_SET_RATE_GATE);
194+
CLK_SET_RATE_GATE, 0);
195195
if (IS_ERR(hw))
196196
goto err_free;
197197

drivers/clk/at91/at91sam9rl.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
132132
"masterck_pres",
133133
&at91rm9200_master_layout,
134134
&sam9rl_mck_characteristics,
135-
&sam9rl_mck_lock, CLK_SET_RATE_GATE);
135+
&sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
136136
if (IS_ERR(hw))
137137
goto err_free;
138138

drivers/clk/at91/at91sam9x5.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
210210
"masterck_pres",
211211
&at91sam9x5_master_layout,
212212
&mck_characteristics, &mck_lock,
213-
CLK_SET_RATE_GATE);
213+
CLK_SET_RATE_GATE, 0);
214214
if (IS_ERR(hw))
215215
goto err_free;
216216

drivers/clk/at91/clk-generated.c

Lines changed: 37 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -27,32 +27,43 @@ struct clk_generated {
2727
u32 id;
2828
u32 gckdiv;
2929
const struct clk_pcr_layout *layout;
30+
struct at91_clk_pms pms;
3031
u8 parent_id;
3132
int chg_pid;
3233
};
3334

3435
#define to_clk_generated(hw) \
3536
container_of(hw, struct clk_generated, hw)
3637

37-
static int clk_generated_enable(struct clk_hw *hw)
38+
static int clk_generated_set(struct clk_generated *gck, int status)
3839
{
39-
struct clk_generated *gck = to_clk_generated(hw);
4040
unsigned long flags;
41-
42-
pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
43-
__func__, gck->gckdiv, gck->parent_id);
41+
unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;
4442

4543
spin_lock_irqsave(gck->lock, flags);
4644
regmap_write(gck->regmap, gck->layout->offset,
4745
(gck->id & gck->layout->pid_mask));
4846
regmap_update_bits(gck->regmap, gck->layout->offset,
4947
AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
50-
gck->layout->cmd | AT91_PMC_PCR_GCKEN,
48+
gck->layout->cmd | enable,
5149
field_prep(gck->layout->gckcss_mask, gck->parent_id) |
5250
gck->layout->cmd |
5351
FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
54-
AT91_PMC_PCR_GCKEN);
52+
enable);
5553
spin_unlock_irqrestore(gck->lock, flags);
54+
55+
return 0;
56+
}
57+
58+
static int clk_generated_enable(struct clk_hw *hw)
59+
{
60+
struct clk_generated *gck = to_clk_generated(hw);
61+
62+
pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
63+
__func__, gck->gckdiv, gck->parent_id);
64+
65+
clk_generated_set(gck, 1);
66+
5667
return 0;
5768
}
5869

@@ -245,6 +256,23 @@ static int clk_generated_set_rate(struct clk_hw *hw,
245256
return 0;
246257
}
247258

259+
static int clk_generated_save_context(struct clk_hw *hw)
260+
{
261+
struct clk_generated *gck = to_clk_generated(hw);
262+
263+
gck->pms.status = clk_generated_is_enabled(&gck->hw);
264+
265+
return 0;
266+
}
267+
268+
static void clk_generated_restore_context(struct clk_hw *hw)
269+
{
270+
struct clk_generated *gck = to_clk_generated(hw);
271+
272+
if (gck->pms.status)
273+
clk_generated_set(gck, gck->pms.status);
274+
}
275+
248276
static const struct clk_ops generated_ops = {
249277
.enable = clk_generated_enable,
250278
.disable = clk_generated_disable,
@@ -254,6 +282,8 @@ static const struct clk_ops generated_ops = {
254282
.get_parent = clk_generated_get_parent,
255283
.set_parent = clk_generated_set_parent,
256284
.set_rate = clk_generated_set_rate,
285+
.save_context = clk_generated_save_context,
286+
.restore_context = clk_generated_restore_context,
257287
};
258288

259289
/**
@@ -320,8 +350,6 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
320350
if (ret) {
321351
kfree(gck);
322352
hw = ERR_PTR(ret);
323-
} else {
324-
pmc_register_id(id);
325353
}
326354

327355
return hw;

drivers/clk/at91/clk-main.c

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
struct clk_main_osc {
2929
struct clk_hw hw;
3030
struct regmap *regmap;
31+
struct at91_clk_pms pms;
3132
};
3233

3334
#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
@@ -37,6 +38,7 @@ struct clk_main_rc_osc {
3738
struct regmap *regmap;
3839
unsigned long frequency;
3940
unsigned long accuracy;
41+
struct at91_clk_pms pms;
4042
};
4143

4244
#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
@@ -51,6 +53,7 @@ struct clk_rm9200_main {
5153
struct clk_sam9x5_main {
5254
struct clk_hw hw;
5355
struct regmap *regmap;
56+
struct at91_clk_pms pms;
5457
u8 parent;
5558
};
5659

@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(struct clk_hw *hw)
120123
return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
121124
}
122125

126+
static int clk_main_osc_save_context(struct clk_hw *hw)
127+
{
128+
struct clk_main_osc *osc = to_clk_main_osc(hw);
129+
130+
osc->pms.status = clk_main_osc_is_prepared(hw);
131+
132+
return 0;
133+
}
134+
135+
static void clk_main_osc_restore_context(struct clk_hw *hw)
136+
{
137+
struct clk_main_osc *osc = to_clk_main_osc(hw);
138+
139+
if (osc->pms.status)
140+
clk_main_osc_prepare(hw);
141+
}
142+
123143
static const struct clk_ops main_osc_ops = {
124144
.prepare = clk_main_osc_prepare,
125145
.unprepare = clk_main_osc_unprepare,
126146
.is_prepared = clk_main_osc_is_prepared,
147+
.save_context = clk_main_osc_save_context,
148+
.restore_context = clk_main_osc_restore_context,
127149
};
128150

129151
struct clk_hw * __init
@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
240262
return osc->accuracy;
241263
}
242264

265+
static int clk_main_rc_osc_save_context(struct clk_hw *hw)
266+
{
267+
struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
268+
269+
osc->pms.status = clk_main_rc_osc_is_prepared(hw);
270+
271+
return 0;
272+
}
273+
274+
static void clk_main_rc_osc_restore_context(struct clk_hw *hw)
275+
{
276+
struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
277+
278+
if (osc->pms.status)
279+
clk_main_rc_osc_prepare(hw);
280+
}
281+
243282
static const struct clk_ops main_rc_osc_ops = {
244283
.prepare = clk_main_rc_osc_prepare,
245284
.unprepare = clk_main_rc_osc_unprepare,
246285
.is_prepared = clk_main_rc_osc_is_prepared,
247286
.recalc_rate = clk_main_rc_osc_recalc_rate,
248287
.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
288+
.save_context = clk_main_rc_osc_save_context,
289+
.restore_context = clk_main_rc_osc_restore_context,
249290
};
250291

251292
struct clk_hw * __init
@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
465506
return clk_main_parent_select(status);
466507
}
467508

509+
static int clk_sam9x5_main_save_context(struct clk_hw *hw)
510+
{
511+
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
512+
513+
clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw);
514+
clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw);
515+
516+
return 0;
517+
}
518+
519+
static void clk_sam9x5_main_restore_context(struct clk_hw *hw)
520+
{
521+
struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
522+
int ret;
523+
524+
ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent);
525+
if (ret)
526+
return;
527+
528+
if (clkmain->pms.status)
529+
clk_sam9x5_main_prepare(hw);
530+
}
531+
468532
static const struct clk_ops sam9x5_main_ops = {
469533
.prepare = clk_sam9x5_main_prepare,
470534
.is_prepared = clk_sam9x5_main_is_prepared,
471535
.recalc_rate = clk_sam9x5_main_recalc_rate,
472536
.set_parent = clk_sam9x5_main_set_parent,
473537
.get_parent = clk_sam9x5_main_get_parent,
538+
.save_context = clk_sam9x5_main_save_context,
539+
.restore_context = clk_sam9x5_main_restore_context,
474540
};
475541

476542
struct clk_hw * __init

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