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Merge branches 'clk-qcom', 'clk-mtk', 'clk-versatile' and 'clk-doc' into clk-next
 - Use ARRAY_SIZE in qcom clk drivers - Remove some impractical fallback parent names in qcom clk drivers - GCC and RPMcc support for Qualcomm QCM2290 SoCs - GCC support for Qualcomm MSM8994/MSM8992 SoCs - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs - Support for Mediatek MT8195 SoCs - Make Mediatek clk drivers tristate * clk-qcom: (44 commits) clk: qcom: gdsc: enable optional power domain support clk: qcom: videocc-sm8250: use runtime PM for the clock controller clk: qcom: dispcc-sm8250: use runtime PM for the clock controller dt-bindings: clock: qcom,videocc: add mmcx power domain dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain clk: qcom: gcc-sc7280: Drop unused array clk: qcom: camcc: Add camera clock controller driver for SC7280 dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280 clk: qcom: Add lpass clock controller driver for SC7280 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180 clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdsc clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdsc clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents clk: qcom: gcc-msm8994: Add proper msm8992 support clk: qcom: gcc-msm8994: Add modem reset clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE clk: qcom: gcc-msm8994: Add missing clocks clk: qcom: gcc-msm8994: Add missing NoC clocks clk: qcom: gcc-msm8994: Fix up SPI QUP clocks ... * clk-mtk: (28 commits) clk: mediatek: Export clk_ops structures to modules clk: mediatek: support COMMON_CLK_MT6779 module build clk: mediatek: support COMMON_CLK_MEDIATEK module build clk: composite: export clk_register_composite clk: mediatek: Add MT8195 apusys clock support clk: mediatek: Add MT8195 imp i2c wrapper clock support clk: mediatek: Add MT8195 wpesys clock support clk: mediatek: Add MT8195 vppsys1 clock support clk: mediatek: Add MT8195 vppsys0 clock support clk: mediatek: Add MT8195 vencsys clock support clk: mediatek: Add MT8195 vdosys1 clock support clk: mediatek: Add MT8195 vdosys0 clock support clk: mediatek: Add MT8195 vdecsys clock support clk: mediatek: Add MT8195 scp adsp clock support clk: mediatek: Add MT8195 mfgcfg clock support clk: mediatek: Add MT8195 ipesys clock support clk: mediatek: Add MT8195 imgsys clock support clk: mediatek: Add MT8195 ccusys clock support clk: mediatek: Add MT8195 camsys clock support clk: mediatek: Add MT8195 infrastructure clock support ... * clk-versatile: clk: versatile: hide clock drivers from non-ARM users clk: versatile: Rename ICST to CLK_ICST clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address dt-bindings: clock: arm,syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address * clk-doc: dt-bindings: clk: fixed-mmio-clock: Convert to YAML
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‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek Functional Clock Controller for MT8195
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maintainers:
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- Chun-Jie Chen <[email protected]>
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description:
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The clock architecture in Mediatek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The devices except apusys_pll provide clock gate control in different IP blocks.
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The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8195-scp_adsp
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- mediatek,mt8195-imp_iic_wrap_s
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- mediatek,mt8195-imp_iic_wrap_w
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- mediatek,mt8195-mfgcfg
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- mediatek,mt8195-vppsys0
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- mediatek,mt8195-wpesys
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- mediatek,mt8195-wpesys_vpp0
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- mediatek,mt8195-wpesys_vpp1
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- mediatek,mt8195-vppsys1
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- mediatek,mt8195-imgsys
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- mediatek,mt8195-imgsys1_dip_top
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- mediatek,mt8195-imgsys1_dip_nr
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- mediatek,mt8195-imgsys1_wpe
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- mediatek,mt8195-ipesys
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- mediatek,mt8195-camsys
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- mediatek,mt8195-camsys_rawa
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- mediatek,mt8195-camsys_yuva
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- mediatek,mt8195-camsys_rawb
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- mediatek,mt8195-camsys_yuvb
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- mediatek,mt8195-camsys_mraw
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- mediatek,mt8195-ccusys
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- mediatek,mt8195-vdecsys_soc
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- mediatek,mt8195-vdecsys
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- mediatek,mt8195-vdecsys_core1
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- mediatek,mt8195-vencsys
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- mediatek,mt8195-vencsys_core1
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- mediatek,mt8195-apusys_pll
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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scp_adsp: clock-controller@10720000 {
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compatible = "mediatek,mt8195-scp_adsp";
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reg = <0x10720000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_s: clock-controller@11d03000 {
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compatible = "mediatek,mt8195-imp_iic_wrap_s";
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reg = <0x11d03000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_w: clock-controller@11e05000 {
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compatible = "mediatek,mt8195-imp_iic_wrap_w";
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reg = <0x11e05000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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mfgcfg: clock-controller@13fbf000 {
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compatible = "mediatek,mt8195-mfgcfg";
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reg = <0x13fbf000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vppsys0: clock-controller@14000000 {
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compatible = "mediatek,mt8195-vppsys0";
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reg = <0x14000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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wpesys: clock-controller@14e00000 {
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compatible = "mediatek,mt8195-wpesys";
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reg = <0x14e00000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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wpesys_vpp0: clock-controller@14e02000 {
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compatible = "mediatek,mt8195-wpesys_vpp0";
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reg = <0x14e02000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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wpesys_vpp1: clock-controller@14e03000 {
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compatible = "mediatek,mt8195-wpesys_vpp1";
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reg = <0x14e03000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vppsys1: clock-controller@14f00000 {
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compatible = "mediatek,mt8195-vppsys1";
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reg = <0x14f00000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys: clock-controller@15000000 {
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compatible = "mediatek,mt8195-imgsys";
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reg = <0x15000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys1_dip_top: clock-controller@15110000 {
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compatible = "mediatek,mt8195-imgsys1_dip_top";
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reg = <0x15110000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys1_dip_nr: clock-controller@15130000 {
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compatible = "mediatek,mt8195-imgsys1_dip_nr";
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reg = <0x15130000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys1_wpe: clock-controller@15220000 {
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compatible = "mediatek,mt8195-imgsys1_wpe";
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reg = <0x15220000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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ipesys: clock-controller@15330000 {
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compatible = "mediatek,mt8195-ipesys";
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reg = <0x15330000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys: clock-controller@16000000 {
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compatible = "mediatek,mt8195-camsys";
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reg = <0x16000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_rawa: clock-controller@1604f000 {
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compatible = "mediatek,mt8195-camsys_rawa";
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reg = <0x1604f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_yuva: clock-controller@1606f000 {
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compatible = "mediatek,mt8195-camsys_yuva";
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reg = <0x1606f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_rawb: clock-controller@1608f000 {
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compatible = "mediatek,mt8195-camsys_rawb";
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reg = <0x1608f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_yuvb: clock-controller@160af000 {
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compatible = "mediatek,mt8195-camsys_yuvb";
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reg = <0x160af000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_mraw: clock-controller@16140000 {
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compatible = "mediatek,mt8195-camsys_mraw";
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reg = <0x16140000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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ccusys: clock-controller@17200000 {
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compatible = "mediatek,mt8195-ccusys";
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reg = <0x17200000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys_soc: clock-controller@1800f000 {
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compatible = "mediatek,mt8195-vdecsys_soc";
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reg = <0x1800f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys: clock-controller@1802f000 {
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compatible = "mediatek,mt8195-vdecsys";
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reg = <0x1802f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys_core1: clock-controller@1803f000 {
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compatible = "mediatek,mt8195-vdecsys_core1";
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reg = <0x1803f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vencsys: clock-controller@1a000000 {
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compatible = "mediatek,mt8195-vencsys";
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reg = <0x1a000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vencsys_core1: clock-controller@1b000000 {
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compatible = "mediatek,mt8195-vencsys_core1";
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reg = <0x1b000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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apusys_pll: clock-controller@190f3000 {
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compatible = "mediatek,mt8195-apusys_pll";
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reg = <0x190f3000 0x1000>;
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#clock-cells = <1>;
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};

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek System Clock Controller for MT8195
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maintainers:
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- Chun-Jie Chen <[email protected]>
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description:
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The clock architecture in Mediatek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The apmixedsys provides most of PLLs which generated from SoC 26m.
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The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8195-topckgen
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- mediatek,mt8195-infracfg_ao
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- mediatek,mt8195-apmixedsys
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- mediatek,mt8195-pericfg_ao
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8195-topckgen", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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infracfg_ao: syscon@10001000 {
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compatible = "mediatek,mt8195-infracfg_ao", "syscon";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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apmixedsys: syscon@1000c000 {
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compatible = "mediatek,mt8195-apmixedsys", "syscon";
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reg = <0x1000c000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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pericfg_ao: syscon@11003000 {
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compatible = "mediatek,mt8195-pericfg_ao", "syscon";
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reg = <0x11003000 0x1000>;
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#clock-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml

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- arm,impd1-vco1
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- arm,impd1-vco2
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reg:
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maxItems: 1
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description: The VCO register
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clocks:
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description: Parent clock for the ICST VCO
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maxItems: 1
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vco-offset:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description: Offset to the VCO register for the oscillator
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deprecated: true
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required:
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- "#clock-cells"

‎Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt

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