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Merge tag 'samsung-pinctrl-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v6.8 1. New hardware: Add pin controllers for Samsung ExynosAutov920 and Google Tensor GS101. 2. Few DT bindings cleanups: add specific compatibles for each device using generic compatible as fallback. This affects only DTS, no driver changes are needed. 3. Allow setting affinity on non wake-up external GPIO interrupts. Signed-off-by: Linus Walleij <[email protected]>
2 parents 84e769e + 6cf96df commit 915fdc9

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‎Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml

Lines changed: 30 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,27 @@ description: |
2828
2929
properties:
3030
compatible:
31-
enum:
32-
- samsung,s3c2410-wakeup-eint
33-
- samsung,s3c2412-wakeup-eint
34-
- samsung,s3c64xx-wakeup-eint
35-
- samsung,s5pv210-wakeup-eint
36-
- samsung,exynos4210-wakeup-eint
37-
- samsung,exynos7-wakeup-eint
38-
- samsung,exynos850-wakeup-eint
39-
- samsung,exynosautov9-wakeup-eint
31+
oneOf:
32+
- enum:
33+
- samsung,s3c2410-wakeup-eint
34+
- samsung,s3c2412-wakeup-eint
35+
- samsung,s3c64xx-wakeup-eint
36+
- samsung,s5pv210-wakeup-eint
37+
- samsung,exynos4210-wakeup-eint
38+
- samsung,exynos7-wakeup-eint
39+
- samsung,exynosautov920-wakeup-eint
40+
- items:
41+
- enum:
42+
- samsung,exynos5433-wakeup-eint
43+
- samsung,exynos7885-wakeup-eint
44+
- samsung,exynos850-wakeup-eint
45+
- const: samsung,exynos7-wakeup-eint
46+
- items:
47+
- enum:
48+
- google,gs101-wakeup-eint
49+
- samsung,exynosautov9-wakeup-eint
50+
- const: samsung,exynos850-wakeup-eint
51+
- const: samsung,exynos7-wakeup-eint
4052

4153
interrupts:
4254
description:
@@ -79,11 +91,14 @@ allOf:
7991
- if:
8092
properties:
8193
compatible:
82-
contains:
83-
enum:
84-
- samsung,s5pv210-wakeup-eint
85-
- samsung,exynos4210-wakeup-eint
86-
- samsung,exynos7-wakeup-eint
94+
# Match without "contains", to skip newer variants which are still
95+
# compatible with samsung,exynos7-wakeup-eint
96+
enum:
97+
- samsung,s5pv210-wakeup-eint
98+
- samsung,exynos4210-wakeup-eint
99+
- samsung,exynos5433-wakeup-eint
100+
- samsung,exynos7-wakeup-eint
101+
- samsung,exynos7885-wakeup-eint
87102
then:
88103
properties:
89104
interrupts:
@@ -98,7 +113,7 @@ allOf:
98113
contains:
99114
enum:
100115
- samsung,exynos850-wakeup-eint
101-
- samsung,exynosautov9-wakeup-eint
116+
- samsung,exynosautov920-wakeup-eint
102117
then:
103118
properties:
104119
interrupts: false

‎Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ properties:
3535

3636
compatible:
3737
enum:
38+
- google,gs101-pinctrl
3839
- samsung,s3c2412-pinctrl
3940
- samsung,s3c2416-pinctrl
4041
- samsung,s3c2440-pinctrl
@@ -53,6 +54,7 @@ properties:
5354
- samsung,exynos7885-pinctrl
5455
- samsung,exynos850-pinctrl
5556
- samsung,exynosautov9-pinctrl
57+
- samsung,exynosautov920-pinctrl
5658
- tesla,fsd-pinctrl
5759

5860
interrupts:
@@ -313,7 +315,8 @@ examples:
313315
pinctrl-0 = <&initial_alive>;
314316
315317
wakeup-interrupt-controller {
316-
compatible = "samsung,exynos7-wakeup-eint";
318+
compatible = "samsung,exynos5433-wakeup-eint",
319+
"samsung,exynos7-wakeup-eint";
317320
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
318321
};
319322

‎MAINTAINERS

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19227,7 +19227,6 @@ R: Alim Akhtar <[email protected]>
1922719227
L: [email protected]
1922819228
S: Maintained
1922919229
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
19230-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
1923119230
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
1923219231
F: Documentation/devicetree/bindings/clock/samsung,s3c*
1923319232
F: drivers/clk/samsung/

‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

Lines changed: 280 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -726,6 +726,146 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
726726
.num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
727727
};
728728

729+
/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */
730+
static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {
731+
EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28),
732+
EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24),
733+
EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"),
734+
};
735+
736+
/* pin banks of exynosautov920 pin-controller 1 (AUD) */
737+
static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = {
738+
EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28),
739+
EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28),
740+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28),
741+
EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28),
742+
EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28),
743+
EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28),
744+
EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28),
745+
};
746+
747+
/* pin banks of exynosautov920 pin-controller 2 (HSI0) */
748+
static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = {
749+
EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28),
750+
EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24),
751+
};
752+
753+
/* pin banks of exynosautov920 pin-controller 3 (HSI1) */
754+
static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = {
755+
EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28),
756+
};
757+
758+
/* pin banks of exynosautov920 pin-controller 4 (HSI2) */
759+
static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = {
760+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28),
761+
EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28),
762+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28),
763+
EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28),
764+
};
765+
766+
/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */
767+
static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = {
768+
EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24),
769+
};
770+
771+
/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */
772+
static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = {
773+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28),
774+
EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28),
775+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28),
776+
EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28),
777+
EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28),
778+
EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24),
779+
EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24),
780+
EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24),
781+
EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24),
782+
EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28),
783+
};
784+
785+
/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */
786+
static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = {
787+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28),
788+
EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28),
789+
EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24),
790+
EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28),
791+
EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24),
792+
EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24),
793+
EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24),
794+
EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24),
795+
EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28),
796+
};
797+
798+
static const struct samsung_retention_data exynosautov920_retention_data __initconst = {
799+
.regs = NULL,
800+
.nr_regs = 0,
801+
.value = 0,
802+
.refcnt = &exynos_shared_retention_refcnt,
803+
.init = exynos_retention_init,
804+
};
805+
806+
static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
807+
{
808+
/* pin-controller instance 0 ALIVE data */
809+
.pin_banks = exynosautov920_pin_banks0,
810+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
811+
.eint_wkup_init = exynos_eint_wkup_init,
812+
.suspend = exynos_pinctrl_suspend,
813+
.resume = exynos_pinctrl_resume,
814+
.retention_data = &exynosautov920_retention_data,
815+
}, {
816+
/* pin-controller instance 1 AUD data */
817+
.pin_banks = exynosautov920_pin_banks1,
818+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1),
819+
}, {
820+
/* pin-controller instance 2 HSI0 data */
821+
.pin_banks = exynosautov920_pin_banks2,
822+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
823+
.eint_gpio_init = exynos_eint_gpio_init,
824+
.suspend = exynos_pinctrl_suspend,
825+
.resume = exynos_pinctrl_resume,
826+
}, {
827+
/* pin-controller instance 3 HSI1 data */
828+
.pin_banks = exynosautov920_pin_banks3,
829+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
830+
.eint_gpio_init = exynos_eint_gpio_init,
831+
.suspend = exynos_pinctrl_suspend,
832+
.resume = exynos_pinctrl_resume,
833+
}, {
834+
/* pin-controller instance 4 HSI2 data */
835+
.pin_banks = exynosautov920_pin_banks4,
836+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
837+
.eint_gpio_init = exynos_eint_gpio_init,
838+
.suspend = exynos_pinctrl_suspend,
839+
.resume = exynos_pinctrl_resume,
840+
}, {
841+
/* pin-controller instance 5 HSI2UFS data */
842+
.pin_banks = exynosautov920_pin_banks5,
843+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
844+
.eint_gpio_init = exynos_eint_gpio_init,
845+
.suspend = exynos_pinctrl_suspend,
846+
.resume = exynos_pinctrl_resume,
847+
}, {
848+
/* pin-controller instance 6 PERIC0 data */
849+
.pin_banks = exynosautov920_pin_banks6,
850+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
851+
.eint_gpio_init = exynos_eint_gpio_init,
852+
.suspend = exynos_pinctrl_suspend,
853+
.resume = exynos_pinctrl_resume,
854+
}, {
855+
/* pin-controller instance 7 PERIC1 data */
856+
.pin_banks = exynosautov920_pin_banks7,
857+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
858+
.eint_gpio_init = exynos_eint_gpio_init,
859+
.suspend = exynos_pinctrl_suspend,
860+
.resume = exynos_pinctrl_resume,
861+
},
862+
};
863+
864+
const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = {
865+
.ctrl = exynosautov920_pin_ctrl,
866+
.num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
867+
};
868+
729869
/*
730870
* Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
731871
* gpio/pin-mux/pinconfig controllers.
@@ -796,3 +936,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
796936
.ctrl = fsd_pin_ctrl,
797937
.num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
798938
};
939+
940+
/* pin banks of gs101 pin-controller (ALIVE) */
941+
static const struct samsung_pin_bank_data gs101_pin_alive[] = {
942+
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
943+
EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04),
944+
EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08),
945+
EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c),
946+
EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10),
947+
EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14),
948+
EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18),
949+
EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c),
950+
};
951+
952+
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
953+
static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
954+
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00),
955+
EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04),
956+
EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08),
957+
EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c),
958+
};
959+
960+
/* pin banks of gs101 pin-controller (GSACORE) */
961+
static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
962+
EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00),
963+
EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04),
964+
EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08),
965+
};
966+
967+
/* pin banks of gs101 pin-controller (GSACTRL) */
968+
static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
969+
EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00),
970+
};
971+
972+
/* pin banks of gs101 pin-controller (PERIC0) */
973+
static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
974+
EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00),
975+
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
976+
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
977+
EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c),
978+
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
979+
EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14),
980+
EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18),
981+
EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c),
982+
EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20),
983+
EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24),
984+
EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28),
985+
EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c),
986+
EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30),
987+
EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34),
988+
EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38),
989+
EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c),
990+
EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40),
991+
EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44),
992+
EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48),
993+
EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c),
994+
};
995+
996+
/* pin banks of gs101 pin-controller (PERIC1) */
997+
static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
998+
EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00),
999+
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04),
1000+
EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08),
1001+
EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c),
1002+
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10),
1003+
EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14),
1004+
EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18),
1005+
EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c),
1006+
};
1007+
1008+
/* pin banks of gs101 pin-controller (HSI1) */
1009+
static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
1010+
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00),
1011+
EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04),
1012+
};
1013+
1014+
/* pin banks of gs101 pin-controller (HSI2) */
1015+
static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
1016+
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00),
1017+
EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04),
1018+
EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08),
1019+
};
1020+
1021+
static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
1022+
{
1023+
/* pin banks of gs101 pin-controller (ALIVE) */
1024+
.pin_banks = gs101_pin_alive,
1025+
.nr_banks = ARRAY_SIZE(gs101_pin_alive),
1026+
.eint_wkup_init = exynos_eint_wkup_init,
1027+
.suspend = exynos_pinctrl_suspend,
1028+
.resume = exynos_pinctrl_resume,
1029+
}, {
1030+
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
1031+
.pin_banks = gs101_pin_far_alive,
1032+
.nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
1033+
.eint_wkup_init = exynos_eint_wkup_init,
1034+
.suspend = exynos_pinctrl_suspend,
1035+
.resume = exynos_pinctrl_resume,
1036+
}, {
1037+
/* pin banks of gs101 pin-controller (GSACORE) */
1038+
.pin_banks = gs101_pin_gsacore,
1039+
.nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
1040+
}, {
1041+
/* pin banks of gs101 pin-controller (GSACTRL) */
1042+
.pin_banks = gs101_pin_gsactrl,
1043+
.nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
1044+
}, {
1045+
/* pin banks of gs101 pin-controller (PERIC0) */
1046+
.pin_banks = gs101_pin_peric0,
1047+
.nr_banks = ARRAY_SIZE(gs101_pin_peric0),
1048+
.eint_gpio_init = exynos_eint_gpio_init,
1049+
.suspend = exynos_pinctrl_suspend,
1050+
.resume = exynos_pinctrl_resume,
1051+
}, {
1052+
/* pin banks of gs101 pin-controller (PERIC1) */
1053+
.pin_banks = gs101_pin_peric1,
1054+
.nr_banks = ARRAY_SIZE(gs101_pin_peric1),
1055+
.eint_gpio_init = exynos_eint_gpio_init,
1056+
.suspend = exynos_pinctrl_suspend,
1057+
.resume = exynos_pinctrl_resume,
1058+
}, {
1059+
/* pin banks of gs101 pin-controller (HSI1) */
1060+
.pin_banks = gs101_pin_hsi1,
1061+
.nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
1062+
.eint_gpio_init = exynos_eint_gpio_init,
1063+
.suspend = exynos_pinctrl_suspend,
1064+
.resume = exynos_pinctrl_resume,
1065+
}, {
1066+
/* pin banks of gs101 pin-controller (HSI2) */
1067+
.pin_banks = gs101_pin_hsi2,
1068+
.nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
1069+
.eint_gpio_init = exynos_eint_gpio_init,
1070+
.suspend = exynos_pinctrl_suspend,
1071+
.resume = exynos_pinctrl_resume,
1072+
},
1073+
};
1074+
1075+
const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
1076+
.ctrl = gs101_pin_ctrl,
1077+
.num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
1078+
};

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