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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
| 2 | +/* |
| 3 | + * Device Tree file for the AM62P5-SK |
| 4 | + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ |
| 5 | + * |
| 6 | + * Schematics: https://www.ti.com/lit/zip/sprr487 |
| 7 | + */ |
| 8 | + |
| 9 | +/dts-v1/; |
| 10 | + |
| 11 | +#include "k3-am62p5.dtsi" |
| 12 | + |
| 13 | +/ { |
| 14 | + compatible = "ti,am62p5-sk", "ti,am62p5"; |
| 15 | + model = "Texas Instruments AM62P5 SK"; |
| 16 | + |
| 17 | + aliases { |
| 18 | + serial0 = &wkup_uart0; |
| 19 | + serial2 = &main_uart0; |
| 20 | + serial3 = &main_uart1; |
| 21 | + }; |
| 22 | + |
| 23 | + chosen { |
| 24 | + stdout-path = &main_uart0; |
| 25 | + }; |
| 26 | + |
| 27 | + memory@80000000 { |
| 28 | + /* 8G RAM */ |
| 29 | + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, |
| 30 | + <0x00000008 0x80000000 0x00000001 0x80000000>; |
| 31 | + device_type = "memory"; |
| 32 | + }; |
| 33 | + |
| 34 | + reserved-memory { |
| 35 | + #address-cells = <2>; |
| 36 | + #size-cells = <2>; |
| 37 | + ranges; |
| 38 | + |
| 39 | + secure_tfa_ddr: tfa@9e780000 { |
| 40 | + reg = <0x00 0x9e780000 0x00 0x80000>; |
| 41 | + no-map; |
| 42 | + }; |
| 43 | + |
| 44 | + secure_ddr: optee@9e800000 { |
| 45 | + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ |
| 46 | + no-map; |
| 47 | + }; |
| 48 | + |
| 49 | + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { |
| 50 | + compatible = "shared-dma-pool"; |
| 51 | + reg = <0x00 0x9c900000 0x00 0x01e00000>; |
| 52 | + no-map; |
| 53 | + }; |
| 54 | + }; |
| 55 | +}; |
| 56 | + |
| 57 | +&main_pmx0 { |
| 58 | + main_uart0_pins_default: main-uart0-default-pins { |
| 59 | + bootph-all; |
| 60 | + pinctrl-single,pins = < |
| 61 | + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ |
| 62 | + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ |
| 63 | + AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */ |
| 64 | + AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */ |
| 65 | + >; |
| 66 | + }; |
| 67 | + |
| 68 | + main_uart1_pins_default: main-uart1-default-pins { |
| 69 | + bootph-all; |
| 70 | + pinctrl-single,pins = < |
| 71 | + AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */ |
| 72 | + AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */ |
| 73 | + AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */ |
| 74 | + AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */ |
| 75 | + >; |
| 76 | + }; |
| 77 | +}; |
| 78 | + |
| 79 | +&main_uart0 { |
| 80 | + bootph-all; |
| 81 | + pinctrl-names = "default"; |
| 82 | + pinctrl-0 = <&main_uart0_pins_default>; |
| 83 | + status = "okay"; |
| 84 | +}; |
| 85 | + |
| 86 | +&main_uart1 { |
| 87 | + pinctrl-names = "default"; |
| 88 | + pinctrl-0 = <&main_uart1_pins_default>; |
| 89 | + /* Main UART1 is used by TIFS firmware */ |
| 90 | + status = "reserved"; |
| 91 | +}; |
| 92 | + |
| 93 | +&cbass_mcu { |
| 94 | + bootph-all; |
| 95 | +}; |
| 96 | + |
| 97 | +&mcu_pmx0 { |
| 98 | + bootph-all; |
| 99 | + wkup_uart0_pins_default: wkup-uart0-default-pins { |
| 100 | + bootph-all; |
| 101 | + pinctrl-single,pins = < |
| 102 | + AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ |
| 103 | + AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ |
| 104 | + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ |
| 105 | + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ |
| 106 | + >; |
| 107 | + }; |
| 108 | +}; |
| 109 | + |
| 110 | +&wkup_uart0 { |
| 111 | + /* WKUP UART0 is used by DM firmware */ |
| 112 | + bootph-all; |
| 113 | + pinctrl-names = "default"; |
| 114 | + pinctrl-0 = <&wkup_uart0_pins_default>; |
| 115 | + status = "reserved"; |
| 116 | +}; |
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