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288 | 288 | };
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289 | 289 |
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290 | 290 | sdma3: dma-controller@302b0000 {
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291 |
| - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; |
| 291 | + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; |
292 | 292 | reg = <0x302b0000 0x10000>;
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293 | 293 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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294 | 294 | clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
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299 | 299 | };
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300 | 300 |
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301 | 301 | sdma2: dma-controller@302c0000 {
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302 |
| - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; |
| 302 | + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; |
303 | 303 | reg = <0x302c0000 0x10000>;
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304 | 304 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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305 | 305 | clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
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612 | 612 | };
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613 | 613 |
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614 | 614 | sdma1: dma-controller@30bd0000 {
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615 |
| - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; |
| 615 | + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; |
616 | 616 | reg = <0x30bd0000 0x10000>;
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617 | 617 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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618 | 618 | clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
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