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clk: mediatek: Add MT8188 camsys clock support
Add MT8188 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/mediatek/Kconfig

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@@ -692,6 +692,13 @@ config COMMON_CLK_MT8188
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help
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This driver supports MediaTek MT8188 clocks.
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config COMMON_CLK_MT8188_CAMSYS
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tristate "Clock driver for MediaTek MT8188 camsys"
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depends on COMMON_CLK_MT8188_VPPSYS
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default COMMON_CLK_MT8188_VPPSYS
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help
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This driver supports MediaTek MT8188 camsys and camsys_raw clocks.
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config COMMON_CLK_MT8192
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tristate "Clock driver for MediaTek MT8192"
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depends on ARM64 || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

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@@ -102,6 +102,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o
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obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
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clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8188_CAMSYS) += clk-mt8188-cam.o
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obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
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obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
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obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

‎drivers/clk/mediatek/clk-mt8188-cam.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <[email protected]>
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*/
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs cam_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_CAM(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate cam_main_clks[] = {
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GATE_CAM(CLK_CAM_MAIN_LARB13, "cam_main_larb13", "top_cam", 0),
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GATE_CAM(CLK_CAM_MAIN_LARB14, "cam_main_larb14", "top_cam", 1),
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GATE_CAM(CLK_CAM_MAIN_CAM, "cam_main_cam", "top_cam", 2),
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GATE_CAM(CLK_CAM_MAIN_CAM_SUBA, "cam_main_cam_suba", "top_cam", 3),
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GATE_CAM(CLK_CAM_MAIN_CAM_SUBB, "cam_main_cam_subb", "top_cam", 4),
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GATE_CAM(CLK_CAM_MAIN_CAMTG, "cam_main_camtg", "top_cam", 7),
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GATE_CAM(CLK_CAM_MAIN_SENINF, "cam_main_seninf", "top_cam", 8),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVA, "cam_main_gcamsva", "top_cam", 9),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVB, "cam_main_gcamsvb", "top_cam", 10),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVC, "cam_main_gcamsvc", "top_cam", 11),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVD, "cam_main_gcamsvd", "top_cam", 12),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVE, "cam_main_gcamsve", "top_cam", 13),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVF, "cam_main_gcamsvf", "top_cam", 14),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVG, "cam_main_gcamsvg", "top_cam", 15),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVH, "cam_main_gcamsvh", "top_cam", 16),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVI, "cam_main_gcamsvi", "top_cam", 17),
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GATE_CAM(CLK_CAM_MAIN_GCAMSVJ, "cam_main_gcamsvj", "top_cam", 18),
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GATE_CAM(CLK_CAM_MAIN_CAMSV_TOP, "cam_main_camsv", "top_cam", 19),
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GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_A, "cam_main_camsv_cq_a", "top_cam", 20),
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GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_B, "cam_main_camsv_cq_b", "top_cam", 21),
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GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_C, "cam_main_camsv_cq_c", "top_cam", 22),
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GATE_CAM(CLK_CAM_MAIN_FAKE_ENG, "cam_main_fake_eng", "top_cam", 28),
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GATE_CAM(CLK_CAM_MAIN_CAM2MM0_GALS, "cam_main_cam2mm0_gals", "top_cam", 29),
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GATE_CAM(CLK_CAM_MAIN_CAM2MM1_GALS, "cam_main_cam2mm1_gals", "top_cam", 30),
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GATE_CAM(CLK_CAM_MAIN_CAM2SYS_GALS, "cam_main_cam2sys_gals", "top_cam", 31),
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};
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static const struct mtk_gate cam_rawa_clks[] = {
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GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "top_cam", 0),
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GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "top_cam", 1),
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GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "top_cam", 2),
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};
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static const struct mtk_gate cam_rawb_clks[] = {
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GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "top_cam", 0),
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GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "top_cam", 1),
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GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "top_cam", 2),
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};
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static const struct mtk_gate cam_yuva_clks[] = {
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GATE_CAM(CLK_CAM_YUVA_LARBX, "cam_yuva_larbx", "top_cam", 0),
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GATE_CAM(CLK_CAM_YUVA_CAM, "cam_yuva_cam", "top_cam", 1),
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GATE_CAM(CLK_CAM_YUVA_CAMTG, "cam_yuva_camtg", "top_cam", 2),
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};
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static const struct mtk_gate cam_yuvb_clks[] = {
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GATE_CAM(CLK_CAM_YUVB_LARBX, "cam_yuvb_larbx", "top_cam", 0),
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GATE_CAM(CLK_CAM_YUVB_CAM, "cam_yuvb_cam", "top_cam", 1),
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GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2),
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};
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static const struct mtk_clk_desc cam_main_desc = {
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.clks = cam_main_clks,
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.num_clks = ARRAY_SIZE(cam_main_clks),
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};
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static const struct mtk_clk_desc cam_rawa_desc = {
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.clks = cam_rawa_clks,
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.num_clks = ARRAY_SIZE(cam_rawa_clks),
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};
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static const struct mtk_clk_desc cam_rawb_desc = {
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.clks = cam_rawb_clks,
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.num_clks = ARRAY_SIZE(cam_rawb_clks),
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};
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static const struct mtk_clk_desc cam_yuva_desc = {
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.clks = cam_yuva_clks,
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.num_clks = ARRAY_SIZE(cam_yuva_clks),
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};
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static const struct mtk_clk_desc cam_yuvb_desc = {
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.clks = cam_yuvb_clks,
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.num_clks = ARRAY_SIZE(cam_yuvb_clks),
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};
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static const struct of_device_id of_match_clk_mt8188_cam[] = {
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{ .compatible = "mediatek,mt8188-camsys", .data = &cam_main_desc },
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{ .compatible = "mediatek,mt8188-camsys-rawa", .data = &cam_rawa_desc },
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{ .compatible = "mediatek,mt8188-camsys-rawb", .data = &cam_rawb_desc },
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{ .compatible = "mediatek,mt8188-camsys-yuva", .data = &cam_yuva_desc },
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{ .compatible = "mediatek,mt8188-camsys-yuvb", .data = &cam_yuvb_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_cam);
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static struct platform_driver clk_mt8188_cam_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8188-cam",
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.of_match_table = of_match_clk_mt8188_cam,
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},
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};
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module_platform_driver(clk_mt8188_cam_drv);
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MODULE_LICENSE("GPL");

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