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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "This a large collection of clk driver updates and a handful of new SoC clk driver support. We have the usual Qualcomm clk drivers, along with clk drivers for the Sophgo and T-Head vendors, all to support some new SoCs. Nothing in particular stands out to me in the updates. There's the interconnect clk driver which exposes clks as interconnects, crossing subsystems. There's a bunch of janitorial things that are improving drivers in general like kmemdup_array() or fixing error paths. But overall the updates look normal to fix the description data which is usually the stuff that's wrong and/or untested. Core: - Skip gate basic type KUnit tests on s390 due to lack of MMIO emulation New Drivers: - AP sub-system clock controller in the T-Head TH1520 - Sophgo Sophon sg2042 clk driver - Qualcomm SM7150 camera, display and video clk drivers - Qualcomm QCM2290 GPU clk driver - Qualcomm QCS8386/QCS8084 NSS clk driver - Qualcomm SM8650 camera and video drivers Updates: - Add reset support to Airoha EN7581 clk driver - Add MODULE_DESCRIPTIONs to various clk drivers - Introduce helper logic to expose clock controllers as simple interconnect providers - Use the interconnect helper above on Qualcomm ipq9574 - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm X1Elite - Improve error handling in Qualcomm kpss-xcc driver - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const - Export more clocks for Rockchip rk3128 peripherals - Convert Rockchip clk drivers to use kmemdup_array() - Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers - Make qcom_cc_really_probe() take a struct device to allow reuse in non-platform-drivers - Introduce prepare-only branch clock ops in the qcom clk driver to support clocks on buses that take locks - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs - Support Qualcomm Huayra 2290 alpha PLL - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match HS200 support - Add missing PCIe PIPE clocks on Qualcomm IPQ9574 - Fix various configurations and properties in the Qualcomm SA8775P, X1E80100 and SM7280 drivers - Park Qualcomm SM8350 GPU RCGs on XO while disabled - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol - exynos-clkout: Remove usage of of_device_id table as .of_match_table, because the driver is instantiated as MFD cell, not as standalone platform driver. Populated .of_match_table confused people few times to convert the code to device_get_match_data(), which broke the driver - Mark one Samsung UFS clock as critical, because having it off stops the system from shutdown - Use kmemdup_array() when applicable - Remove unused 'struct gates_data' from old sunxi driver library - Add GPADC clock and reset for Allwinner H616 - Minor Amlogic S4 clock fixes - DT bindings Yaml conversion of the Amlogic AXG audio controller - Amlogic C3 clock controllers support - Amlogic clk flag added to skip init of already enabled PLLs and avoid relocking - Amlogic A1 DT bindings updates for system pll support - Add missing MODULE_DESCRIPTION where necessary - Remove obsolete clock DT binding header files - Add Battery Backup (VBATTB) and I2C clocks, resets, and power domains on Renesas RZ/G3S - Add audio clocks on Renesas R-Car V4M - Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits) clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate() clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id() clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate() clk: sunxi-ng r40: Constify struct regmap_config clk: en7523: fix rate divider for slic and spi clocks clk: lpc32xx: Constify struct regmap_config clk: xilinx: Constify struct regmap_config clk: en7523: Remove PCIe reset open drain configuration for EN7581 clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC clk: en7523: Add reset-controller support for EN7581 SoC dt-bindings: clock: airoha: Add reset support to EN7581 clock binding dt-bindings: clock: mediatek: Document reset cells for MT8188 sys clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys dt-bindings: clock: sprd,sc9860-clk: convert to YAML dt-bindings: clock: qoriq-clock: convert to yaml format clk: qcom: Park shared RCGs upon registration clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks ...
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‎Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,14 +35,18 @@ properties:
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reg:
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minItems: 2
38-
maxItems: 3
38+
maxItems: 4
3939

4040
"#clock-cells":
4141
description:
4242
The first cell indicates the clock number, see [1] for available
4343
clocks.
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const: 1
4545

46+
'#reset-cells':
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description: ID of the controller reset line
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const: 1
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4650
required:
4751
- compatible
4852
- reg
@@ -60,6 +64,8 @@ allOf:
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- description: scu base address
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- description: misc scu base address
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'#reset-cells': false
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6369
- if:
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properties:
6571
compatible:
@@ -70,6 +76,7 @@ allOf:
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items:
7177
- description: scu base address
7278
- description: misc scu base address
79+
- description: reset base address
7380
- description: pb scu base address
7481

7582
additionalProperties: false
@@ -83,3 +90,19 @@ examples:
8390
<0x1fb00000 0x1000>;
8491
#clock-cells = <1>;
8592
};
93+
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- |
95+
soc {
96+
#address-cells = <2>;
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#size-cells = <2>;
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scuclk: clock-controller@1fa20000 {
100+
compatible = "airoha,en7581-scu";
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reg = <0x0 0x1fa20000 0x0 0x400>,
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<0x0 0x1fb00000 0x0 0x90>,
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<0x0 0x1fb00830 0x0 0x8>,
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<0x0 0x1fbe3400 0x0 0xfc>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};

‎Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@ properties:
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- description: input fixed pll div7
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- description: input hifi pll
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- description: input oscillator (usually at 24MHz)
33+
- description: input sys pll
34+
minItems: 6 # sys_pll is optional
3335

3436
clock-names:
3537
items:
@@ -39,6 +41,8 @@ properties:
3941
- const: fclk_div7
4042
- const: hifi_pll
4143
- const: xtal
44+
- const: sys_pll
45+
minItems: 6 # sys_pll is optional
4246

4347
required:
4448
- compatible
@@ -65,9 +69,10 @@ examples:
6569
<&clkc_pll CLKID_FCLK_DIV5>,
6670
<&clkc_pll CLKID_FCLK_DIV7>,
6771
<&clkc_pll CLKID_HIFI_PLL>,
68-
<&xtal>;
72+
<&xtal>,
73+
<&clkc_pll CLKID_SYS_PLL>;
6974
clock-names = "fclk_div2", "fclk_div3",
7075
"fclk_div5", "fclk_div7",
71-
"hifi_pll", "xtal";
76+
"hifi_pll", "xtal", "sys_pll";
7277
};
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};

‎Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,11 +26,15 @@ properties:
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items:
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- description: input fixpll_in
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- description: input hifipll_in
29+
- description: input syspll_in
30+
minItems: 2 # syspll_in is optional
2931

3032
clock-names:
3133
items:
3234
- const: fixpll_in
3335
- const: hifipll_in
36+
- const: syspll_in
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minItems: 2 # syspll_in is optional
3438

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required:
3640
- compatible
@@ -53,7 +57,8 @@ examples:
5357
reg = <0 0x7c80 0 0x18c>;
5458
#clock-cells = <1>;
5559
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
56-
<&clkc_periphs CLKID_HIFIPLL_IN>;
57-
clock-names = "fixpll_in", "hifipll_in";
60+
<&clkc_periphs CLKID_HIFIPLL_IN>,
61+
<&clkc_periphs CLKID_SYSPLL_IN>;
62+
clock-names = "fixpll_in", "hifipll_in", "syspll_in";
5863
};
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};

‎Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

Lines changed: 0 additions & 59 deletions
This file was deleted.

‎Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,201 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Amlogic AXG Audio Clock Controller
8+
9+
maintainers:
10+
- Neil Armstrong <[email protected]>
11+
- Jerome Brunet <[email protected]>
12+
13+
description:
14+
The Amlogic AXG audio clock controller generates and supplies clock to the
15+
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
16+
devices.
17+
18+
properties:
19+
compatible:
20+
enum:
21+
- amlogic,axg-audio-clkc
22+
- amlogic,g12a-audio-clkc
23+
- amlogic,sm1-audio-clkc
24+
25+
'#clock-cells':
26+
const: 1
27+
28+
'#reset-cells':
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const: 1
30+
31+
reg:
32+
maxItems: 1
33+
34+
clocks:
35+
minItems: 1
36+
items:
37+
- description: main peripheral bus clock
38+
- description: input plls to generate clock signals N0
39+
- description: input plls to generate clock signals N1
40+
- description: input plls to generate clock signals N2
41+
- description: input plls to generate clock signals N3
42+
- description: input plls to generate clock signals N4
43+
- description: input plls to generate clock signals N5
44+
- description: input plls to generate clock signals N6
45+
- description: input plls to generate clock signals N7
46+
- description: slave bit clock N0 provided by external components
47+
- description: slave bit clock N1 provided by external components
48+
- description: slave bit clock N2 provided by external components
49+
- description: slave bit clock N3 provided by external components
50+
- description: slave bit clock N4 provided by external components
51+
- description: slave bit clock N5 provided by external components
52+
- description: slave bit clock N6 provided by external components
53+
- description: slave bit clock N7 provided by external components
54+
- description: slave bit clock N8 provided by external components
55+
- description: slave bit clock N9 provided by external components
56+
- description: slave sample clock N0 provided by external components
57+
- description: slave sample clock N1 provided by external components
58+
- description: slave sample clock N2 provided by external components
59+
- description: slave sample clock N3 provided by external components
60+
- description: slave sample clock N4 provided by external components
61+
- description: slave sample clock N5 provided by external components
62+
- description: slave sample clock N6 provided by external components
63+
- description: slave sample clock N7 provided by external components
64+
- description: slave sample clock N8 provided by external components
65+
- description: slave sample clock N9 provided by external components
66+
67+
clock-names:
68+
minItems: 1
69+
items:
70+
- const: pclk
71+
- const: mst_in0
72+
- const: mst_in1
73+
- const: mst_in2
74+
- const: mst_in3
75+
- const: mst_in4
76+
- const: mst_in5
77+
- const: mst_in6
78+
- const: mst_in7
79+
- const: slv_sclk0
80+
- const: slv_sclk1
81+
- const: slv_sclk2
82+
- const: slv_sclk3
83+
- const: slv_sclk4
84+
- const: slv_sclk5
85+
- const: slv_sclk6
86+
- const: slv_sclk7
87+
- const: slv_sclk8
88+
- const: slv_sclk9
89+
- const: slv_lrclk0
90+
- const: slv_lrclk1
91+
- const: slv_lrclk2
92+
- const: slv_lrclk3
93+
- const: slv_lrclk4
94+
- const: slv_lrclk5
95+
- const: slv_lrclk6
96+
- const: slv_lrclk7
97+
- const: slv_lrclk8
98+
- const: slv_lrclk9
99+
100+
resets:
101+
description: internal reset line
102+
103+
required:
104+
- compatible
105+
- '#clock-cells'
106+
- reg
107+
- clocks
108+
- clock-names
109+
- resets
110+
111+
allOf:
112+
- if:
113+
properties:
114+
compatible:
115+
contains:
116+
enum:
117+
- amlogic,g12a-audio-clkc
118+
- amlogic,sm1-audio-clkc
119+
then:
120+
required:
121+
- '#reset-cells'
122+
else:
123+
properties:
124+
'#reset-cells': false
125+
126+
additionalProperties: false
127+
128+
examples:
129+
- |
130+
#include <dt-bindings/clock/axg-clkc.h>
131+
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
132+
apb {
133+
#address-cells = <2>;
134+
#size-cells = <2>;
135+
136+
clkc_audio: clock-controller@0 {
137+
compatible = "amlogic,axg-audio-clkc";
138+
reg = <0x0 0x0 0x0 0xb4>;
139+
#clock-cells = <1>;
140+
141+
clocks = <&clkc CLKID_AUDIO>,
142+
<&clkc CLKID_MPLL0>,
143+
<&clkc CLKID_MPLL1>,
144+
<&clkc CLKID_MPLL2>,
145+
<&clkc CLKID_MPLL3>,
146+
<&clkc CLKID_HIFI_PLL>,
147+
<&clkc CLKID_FCLK_DIV3>,
148+
<&clkc CLKID_FCLK_DIV4>,
149+
<&clkc CLKID_GP0_PLL>,
150+
<&slv_sclk0>,
151+
<&slv_sclk1>,
152+
<&slv_sclk2>,
153+
<&slv_sclk3>,
154+
<&slv_sclk4>,
155+
<&slv_sclk5>,
156+
<&slv_sclk6>,
157+
<&slv_sclk7>,
158+
<&slv_sclk8>,
159+
<&slv_sclk9>,
160+
<&slv_lrclk0>,
161+
<&slv_lrclk1>,
162+
<&slv_lrclk2>,
163+
<&slv_lrclk3>,
164+
<&slv_lrclk4>,
165+
<&slv_lrclk5>,
166+
<&slv_lrclk6>,
167+
<&slv_lrclk7>,
168+
<&slv_lrclk8>,
169+
<&slv_lrclk9>;
170+
clock-names = "pclk",
171+
"mst_in0",
172+
"mst_in1",
173+
"mst_in2",
174+
"mst_in3",
175+
"mst_in4",
176+
"mst_in5",
177+
"mst_in6",
178+
"mst_in7",
179+
"slv_sclk0",
180+
"slv_sclk1",
181+
"slv_sclk2",
182+
"slv_sclk3",
183+
"slv_sclk4",
184+
"slv_sclk5",
185+
"slv_sclk6",
186+
"slv_sclk7",
187+
"slv_sclk8",
188+
"slv_sclk9",
189+
"slv_lrclk0",
190+
"slv_lrclk1",
191+
"slv_lrclk2",
192+
"slv_lrclk3",
193+
"slv_lrclk4",
194+
"slv_lrclk5",
195+
"slv_lrclk6",
196+
"slv_lrclk7",
197+
"slv_lrclk8",
198+
"slv_lrclk9";
199+
resets = <&reset RESET_AUDIO>;
200+
};
201+
};

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