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Sowjanya Komatinenithierryreding
Sowjanya Komatineni
authored and
thierryreding
committed
clk: tegra: Remove tegra_pmc_clk_init along with clk ids
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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9 files changed

+19
-201
lines changed

9 files changed

+19
-201
lines changed

‎drivers/clk/tegra/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@ obj-y += clk-sdmmc-mux.o
1212
obj-y += clk-super.o
1313
obj-y += clk-tegra-audio.o
1414
obj-y += clk-tegra-periph.o
15-
obj-y += clk-tegra-pmc.o
1615
obj-y += clk-tegra-fixed.o
1716
obj-y += clk-tegra-super-gen4.o
1817
obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o

‎drivers/clk/tegra/clk-id.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ enum clk_id {
3232
tegra_clk_audio4,
3333
tegra_clk_audio4_2x,
3434
tegra_clk_audio4_mux,
35-
tegra_clk_blink,
3635
tegra_clk_bsea,
3736
tegra_clk_bsev,
3837
tegra_clk_cclk_g,
@@ -47,12 +46,6 @@ enum clk_id {
4746
tegra_clk_osc,
4847
tegra_clk_osc_div2,
4948
tegra_clk_osc_div4,
50-
tegra_clk_clk_out_1,
51-
tegra_clk_clk_out_1_mux,
52-
tegra_clk_clk_out_2,
53-
tegra_clk_clk_out_2_mux,
54-
tegra_clk_clk_out_3,
55-
tegra_clk_clk_out_3_mux,
5649
tegra_clk_cml0,
5750
tegra_clk_cml1,
5851
tegra_clk_csi,

‎drivers/clk/tegra/clk-tegra-pmc.c

Lines changed: 0 additions & 122 deletions
This file was deleted.

‎drivers/clk/tegra/clk-tegra114.c

Lines changed: 3 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -779,10 +779,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
779779
[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
780780
[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
781781
[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
782-
[tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
783-
[tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
784-
[tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
785-
[tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
786782
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
787783
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
788784
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
@@ -804,9 +800,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
804800
[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
805801
[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
806802
[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
807-
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
808-
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
809-
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
810803
[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
811804
[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
812805
[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
@@ -865,10 +858,9 @@ static struct tegra_devclk devclks[] __initdata = {
865858
{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
866859
{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
867860
{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
868-
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
869-
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
870-
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
871-
{ .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
861+
{ .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
862+
{ .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
863+
{ .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
872864
{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
873865
{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
874866
{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
@@ -1147,8 +1139,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
11471139
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
11481140
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
11491141
{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
1150-
{ TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
1151-
{ TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
11521142
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
11531143
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
11541144
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1350,7 +1340,6 @@ static void __init tegra114_clock_init(struct device_node *np)
13501340
tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
13511341
tegra114_audio_plls,
13521342
ARRAY_SIZE(tegra114_audio_plls), 24000000);
1353-
tegra_pmc_clk_init(pmc_base, tegra114_clks);
13541343
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
13551344
&pll_x_params);
13561345

‎drivers/clk/tegra/clk-tegra124.c

Lines changed: 10 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -903,10 +903,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
903903
[tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
904904
[tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
905905
[tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
906-
[tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
907-
[tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
908-
[tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
909-
[tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
910906
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
911907
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
912908
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
@@ -932,9 +928,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
932928
[tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
933929
[tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
934930
[tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
935-
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
936-
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
937-
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
938931
[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
939932
};
940933

@@ -990,10 +983,9 @@ static struct tegra_devclk devclks[] __initdata = {
990983
{ .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
991984
{ .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
992985
{ .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
993-
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
994-
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
995-
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
996-
{ .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
986+
{ .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
987+
{ .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
988+
{ .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
997989
{ .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
998990
{ .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
999991
{ .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
@@ -1303,8 +1295,6 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
13031295
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
13041296
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
13051297
{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
1306-
{ TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
1307-
{ TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
13081298
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
13091299
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
13101300
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1459,11 +1449,9 @@ static void __init tegra132_clock_apply_init_table(void)
14591449
* tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
14601450
* @np: struct device_node * of the DT node for the SoC CAR IP block
14611451
*
1462-
* Register most of the clocks controlled by the CAR IP block, along
1463-
* with a few clocks controlled by the PMC IP block. Everything in
1464-
* this function should be common to Tegra124 and Tegra132. XXX The
1465-
* PMC clock initialization should probably be moved to PMC-specific
1466-
* driver code. No return value.
1452+
* Register most of the clocks controlled by the CAR IP block.
1453+
* Everything in this function should be common to Tegra124 and Tegra132.
1454+
* No return value.
14671455
*/
14681456
static void __init tegra124_132_clock_init_pre(struct device_node *np)
14691457
{
@@ -1506,7 +1494,6 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
15061494
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
15071495
tegra124_audio_plls,
15081496
ARRAY_SIZE(tegra124_audio_plls), 24576000);
1509-
tegra_pmc_clk_init(pmc_base, tegra124_clks);
15101497

15111498
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
15121499
plld_base = readl(clk_base + PLLD_BASE);
@@ -1518,11 +1505,11 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
15181505
* tegra124_132_clock_init_post - clock initialization postamble for T124/T132
15191506
* @np: struct device_node * of the DT node for the SoC CAR IP block
15201507
*
1521-
* Register most of the along with a few clocks controlled by the PMC
1522-
* IP block. Everything in this function should be common to Tegra124
1508+
* Register most of the clocks controlled by the CAR IP block.
1509+
* Everything in this function should be common to Tegra124
15231510
* and Tegra132. This function must be called after
1524-
* tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1525-
* not be set. No return value.
1511+
* tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
1512+
* No return value.
15261513
*/
15271514
static void __init tegra124_132_clock_init_post(struct device_node *np)
15281515
{

‎drivers/clk/tegra/clk-tegra20.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,6 @@ static struct tegra_devclk devclks[] __initdata = {
458458
{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
459459
{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
460460
{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
461-
{ .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
462461
{ .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
463462
{ .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
464463
{ .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
@@ -537,7 +536,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
537536
[tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
538537
[tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
539538
[tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
540-
[tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
541539
[tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
542540
[tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
543541
[tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
@@ -1034,7 +1032,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
10341032
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
10351033
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
10361034
{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
1037-
{ TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
10381035
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
10391036
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
10401037
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
@@ -1146,7 +1143,6 @@ static void __init tegra20_clock_init(struct device_node *np)
11461143
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
11471144
tegra20_periph_clk_init();
11481145
tegra20_audio_clk_init();
1149-
tegra_pmc_clk_init(pmc_base, tegra20_clks);
11501146

11511147
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
11521148

‎drivers/clk/tegra/clk-tegra210.c

Lines changed: 3 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2418,10 +2418,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
24182418
[tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
24192419
[tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
24202420
[tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2421-
[tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
2422-
[tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
2423-
[tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
2424-
[tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
24252421
[tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
24262422
[tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
24272423
[tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
@@ -2453,9 +2449,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
24532449
[tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
24542450
[tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
24552451
[tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2456-
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
2457-
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
2458-
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
24592452
[tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
24602453
[tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
24612454
[tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
@@ -2542,10 +2535,9 @@ static struct tegra_devclk devclks[] __initdata = {
25422535
{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
25432536
{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
25442537
{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2545-
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
2546-
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
2547-
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
2548-
{ .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
2538+
{ .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
2539+
{ .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
2540+
{ .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
25492541
{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
25502542
{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
25512543
{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
@@ -3453,8 +3445,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
34533445
{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
34543446
{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
34553447
{ TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
3456-
{ TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
3457-
{ TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
34583448
{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
34593449
{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
34603450
{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -3695,7 +3685,6 @@ static void __init tegra210_clock_init(struct device_node *np)
36953685
tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
36963686
tegra210_audio_plls,
36973687
ARRAY_SIZE(tegra210_audio_plls), 24576000);
3698-
tegra_pmc_clk_init(pmc_base, tegra210_clks);
36993688

37003689
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
37013690
value = readl(clk_base + PLLD_BASE);

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