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Merge branch 'clk-amlogic' into clk-next
* clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2 parents fca1484 + bfd35bf commit b396b3d

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5 files changed

+180
-19
lines changed

5 files changed

+180
-19
lines changed

‎drivers/clk/meson/g12a.c

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3981,6 +3981,113 @@ static struct clk_regmap g12a_spicc1_sclk = {
39813981
},
39823982
};
39833983

3984+
/* Neural Network Accelerator source clock */
3985+
3986+
static const struct clk_parent_data nna_clk_parent_data[] = {
3987+
{ .fw_name = "xtal", },
3988+
{ .hw = &g12a_gp0_pll.hw, },
3989+
{ .hw = &g12a_hifi_pll.hw, },
3990+
{ .hw = &g12a_fclk_div2p5.hw, },
3991+
{ .hw = &g12a_fclk_div3.hw, },
3992+
{ .hw = &g12a_fclk_div4.hw, },
3993+
{ .hw = &g12a_fclk_div5.hw, },
3994+
{ .hw = &g12a_fclk_div7.hw },
3995+
};
3996+
3997+
static struct clk_regmap sm1_nna_axi_clk_sel = {
3998+
.data = &(struct clk_regmap_mux_data){
3999+
.offset = HHI_NNA_CLK_CNTL,
4000+
.mask = 7,
4001+
.shift = 9,
4002+
},
4003+
.hw.init = &(struct clk_init_data){
4004+
.name = "nna_axi_clk_sel",
4005+
.ops = &clk_regmap_mux_ops,
4006+
.parent_data = nna_clk_parent_data,
4007+
.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4008+
},
4009+
};
4010+
4011+
static struct clk_regmap sm1_nna_axi_clk_div = {
4012+
.data = &(struct clk_regmap_div_data){
4013+
.offset = HHI_NNA_CLK_CNTL,
4014+
.shift = 0,
4015+
.width = 7,
4016+
},
4017+
.hw.init = &(struct clk_init_data){
4018+
.name = "nna_axi_clk_div",
4019+
.ops = &clk_regmap_divider_ops,
4020+
.parent_hws = (const struct clk_hw *[]) {
4021+
&sm1_nna_axi_clk_sel.hw
4022+
},
4023+
.num_parents = 1,
4024+
.flags = CLK_SET_RATE_PARENT,
4025+
},
4026+
};
4027+
4028+
static struct clk_regmap sm1_nna_axi_clk = {
4029+
.data = &(struct clk_regmap_gate_data){
4030+
.offset = HHI_NNA_CLK_CNTL,
4031+
.bit_idx = 8,
4032+
},
4033+
.hw.init = &(struct clk_init_data){
4034+
.name = "nna_axi_clk",
4035+
.ops = &clk_regmap_gate_ops,
4036+
.parent_hws = (const struct clk_hw *[]) {
4037+
&sm1_nna_axi_clk_div.hw
4038+
},
4039+
.num_parents = 1,
4040+
.flags = CLK_SET_RATE_PARENT,
4041+
},
4042+
};
4043+
4044+
static struct clk_regmap sm1_nna_core_clk_sel = {
4045+
.data = &(struct clk_regmap_mux_data){
4046+
.offset = HHI_NNA_CLK_CNTL,
4047+
.mask = 7,
4048+
.shift = 25,
4049+
},
4050+
.hw.init = &(struct clk_init_data){
4051+
.name = "nna_core_clk_sel",
4052+
.ops = &clk_regmap_mux_ops,
4053+
.parent_data = nna_clk_parent_data,
4054+
.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4055+
},
4056+
};
4057+
4058+
static struct clk_regmap sm1_nna_core_clk_div = {
4059+
.data = &(struct clk_regmap_div_data){
4060+
.offset = HHI_NNA_CLK_CNTL,
4061+
.shift = 16,
4062+
.width = 7,
4063+
},
4064+
.hw.init = &(struct clk_init_data){
4065+
.name = "nna_core_clk_div",
4066+
.ops = &clk_regmap_divider_ops,
4067+
.parent_hws = (const struct clk_hw *[]) {
4068+
&sm1_nna_core_clk_sel.hw
4069+
},
4070+
.num_parents = 1,
4071+
.flags = CLK_SET_RATE_PARENT,
4072+
},
4073+
};
4074+
4075+
static struct clk_regmap sm1_nna_core_clk = {
4076+
.data = &(struct clk_regmap_gate_data){
4077+
.offset = HHI_NNA_CLK_CNTL,
4078+
.bit_idx = 24,
4079+
},
4080+
.hw.init = &(struct clk_init_data){
4081+
.name = "nna_core_clk",
4082+
.ops = &clk_regmap_gate_ops,
4083+
.parent_hws = (const struct clk_hw *[]) {
4084+
&sm1_nna_core_clk_div.hw
4085+
},
4086+
.num_parents = 1,
4087+
.flags = CLK_SET_RATE_PARENT,
4088+
},
4089+
};
4090+
39844091
#define MESON_GATE(_name, _reg, _bit) \
39854092
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
39864093

@@ -4779,6 +4886,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
47794886
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
47804887
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
47814888
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4889+
[CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4890+
[CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4891+
[CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4892+
[CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4893+
[CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4894+
[CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
47824895
[NR_CLKS] = NULL,
47834896
},
47844897
.num = NR_CLKS,
@@ -5020,6 +5133,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
50205133
&g12a_spicc1_sclk_sel,
50215134
&g12a_spicc1_sclk_div,
50225135
&g12a_spicc1_sclk,
5136+
&sm1_nna_axi_clk_sel,
5137+
&sm1_nna_axi_clk_div,
5138+
&sm1_nna_axi_clk,
5139+
&sm1_nna_core_clk_sel,
5140+
&sm1_nna_core_clk_div,
5141+
&sm1_nna_core_clk,
50235142
};
50245143

50255144
static const struct reg_sequence g12a_init_regs[] = {

‎drivers/clk/meson/g12a.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@
7070
#define HHI_MALI_CLK_CNTL 0x1b0
7171
#define HHI_VPU_CLKC_CNTL 0x1b4
7272
#define HHI_VPU_CLK_CNTL 0x1bC
73+
#define HHI_NNA_CLK_CNTL 0x1C8
7374
#define HHI_HDMI_CLK_CNTL 0x1CC
7475
#define HHI_VDEC_CLK_CNTL 0x1E0
7576
#define HHI_VDEC2_CLK_CNTL 0x1E4
@@ -259,8 +260,12 @@
259260
#define CLKID_SPICC0_SCLK_DIV 257
260261
#define CLKID_SPICC1_SCLK_SEL 259
261262
#define CLKID_SPICC1_SCLK_DIV 260
263+
#define CLKID_NNA_AXI_CLK_SEL 262
264+
#define CLKID_NNA_AXI_CLK_DIV 263
265+
#define CLKID_NNA_CORE_CLK_SEL 265
266+
#define CLKID_NNA_CORE_CLK_DIV 266
262267

263-
#define NR_CLKS 262
268+
#define NR_CLKS 268
264269

265270
/* include the CLKIDs that have been made part of the DT binding */
266271
#include <dt-bindings/clock/g12a-clkc.h>

‎drivers/clk/meson/meson8b.c

Lines changed: 50 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = {
293293
&meson8b_fclk_div2_div.hw
294294
},
295295
.num_parents = 1,
296-
/*
297-
* FIXME: Ethernet with a RGMII PHYs is not working if
298-
* fclk_div2 is disabled. it is currently unclear why this
299-
* is. keep it enabled until the Ethernet driver knows how
300-
* to manage this clock.
301-
*/
302-
.flags = CLK_IS_CRITICAL,
303296
},
304297
};
305298

@@ -1211,6 +1204,22 @@ static struct clk_regmap meson8b_vclk_in_en = {
12111204
},
12121205
};
12131206

1207+
static struct clk_regmap meson8b_vclk_en = {
1208+
.data = &(struct clk_regmap_gate_data){
1209+
.offset = HHI_VID_CLK_CNTL,
1210+
.bit_idx = 19,
1211+
},
1212+
.hw.init = &(struct clk_init_data){
1213+
.name = "vclk_en",
1214+
.ops = &clk_regmap_gate_ro_ops,
1215+
.parent_hws = (const struct clk_hw *[]) {
1216+
&meson8b_vclk_in_en.hw
1217+
},
1218+
.num_parents = 1,
1219+
.flags = CLK_SET_RATE_PARENT,
1220+
},
1221+
};
1222+
12141223
static struct clk_regmap meson8b_vclk_div1_gate = {
12151224
.data = &(struct clk_regmap_gate_data){
12161225
.offset = HHI_VID_CLK_CNTL,
@@ -1220,7 +1229,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
12201229
.name = "vclk_div1_en",
12211230
.ops = &clk_regmap_gate_ro_ops,
12221231
.parent_hws = (const struct clk_hw *[]) {
1223-
&meson8b_vclk_in_en.hw
1232+
&meson8b_vclk_en.hw
12241233
},
12251234
.num_parents = 1,
12261235
.flags = CLK_SET_RATE_PARENT,
@@ -1234,7 +1243,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
12341243
.name = "vclk_div2",
12351244
.ops = &clk_fixed_factor_ops,
12361245
.parent_hws = (const struct clk_hw *[]) {
1237-
&meson8b_vclk_in_en.hw
1246+
&meson8b_vclk_en.hw
12381247
},
12391248
.num_parents = 1,
12401249
.flags = CLK_SET_RATE_PARENT,
@@ -1264,7 +1273,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
12641273
.name = "vclk_div4",
12651274
.ops = &clk_fixed_factor_ops,
12661275
.parent_hws = (const struct clk_hw *[]) {
1267-
&meson8b_vclk_in_en.hw
1276+
&meson8b_vclk_en.hw
12681277
},
12691278
.num_parents = 1,
12701279
.flags = CLK_SET_RATE_PARENT,
@@ -1294,7 +1303,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
12941303
.name = "vclk_div6",
12951304
.ops = &clk_fixed_factor_ops,
12961305
.parent_hws = (const struct clk_hw *[]) {
1297-
&meson8b_vclk_in_en.hw
1306+
&meson8b_vclk_en.hw
12981307
},
12991308
.num_parents = 1,
13001309
.flags = CLK_SET_RATE_PARENT,
@@ -1324,7 +1333,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
13241333
.name = "vclk_div12",
13251334
.ops = &clk_fixed_factor_ops,
13261335
.parent_hws = (const struct clk_hw *[]) {
1327-
&meson8b_vclk_in_en.hw
1336+
&meson8b_vclk_en.hw
13281337
},
13291338
.num_parents = 1,
13301339
.flags = CLK_SET_RATE_PARENT,
@@ -1378,6 +1387,22 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
13781387
},
13791388
};
13801389

1390+
static struct clk_regmap meson8b_vclk2_clk_en = {
1391+
.data = &(struct clk_regmap_gate_data){
1392+
.offset = HHI_VIID_CLK_DIV,
1393+
.bit_idx = 19,
1394+
},
1395+
.hw.init = &(struct clk_init_data){
1396+
.name = "vclk2_en",
1397+
.ops = &clk_regmap_gate_ro_ops,
1398+
.parent_hws = (const struct clk_hw *[]) {
1399+
&meson8b_vclk2_clk_in_en.hw
1400+
},
1401+
.num_parents = 1,
1402+
.flags = CLK_SET_RATE_PARENT,
1403+
},
1404+
};
1405+
13811406
static struct clk_regmap meson8b_vclk2_div1_gate = {
13821407
.data = &(struct clk_regmap_gate_data){
13831408
.offset = HHI_VIID_CLK_DIV,
@@ -1387,7 +1412,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
13871412
.name = "vclk2_div1_en",
13881413
.ops = &clk_regmap_gate_ro_ops,
13891414
.parent_hws = (const struct clk_hw *[]) {
1390-
&meson8b_vclk2_clk_in_en.hw
1415+
&meson8b_vclk2_clk_en.hw
13911416
},
13921417
.num_parents = 1,
13931418
.flags = CLK_SET_RATE_PARENT,
@@ -1401,7 +1426,7 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = {
14011426
.name = "vclk2_div2",
14021427
.ops = &clk_fixed_factor_ops,
14031428
.parent_hws = (const struct clk_hw *[]) {
1404-
&meson8b_vclk2_clk_in_en.hw
1429+
&meson8b_vclk2_clk_en.hw
14051430
},
14061431
.num_parents = 1,
14071432
.flags = CLK_SET_RATE_PARENT,
@@ -1431,7 +1456,7 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = {
14311456
.name = "vclk2_div4",
14321457
.ops = &clk_fixed_factor_ops,
14331458
.parent_hws = (const struct clk_hw *[]) {
1434-
&meson8b_vclk2_clk_in_en.hw
1459+
&meson8b_vclk2_clk_en.hw
14351460
},
14361461
.num_parents = 1,
14371462
.flags = CLK_SET_RATE_PARENT,
@@ -1461,7 +1486,7 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = {
14611486
.name = "vclk2_div6",
14621487
.ops = &clk_fixed_factor_ops,
14631488
.parent_hws = (const struct clk_hw *[]) {
1464-
&meson8b_vclk2_clk_in_en.hw
1489+
&meson8b_vclk2_clk_en.hw
14651490
},
14661491
.num_parents = 1,
14671492
.flags = CLK_SET_RATE_PARENT,
@@ -1491,7 +1516,7 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = {
14911516
.name = "vclk2_div12",
14921517
.ops = &clk_fixed_factor_ops,
14931518
.parent_hws = (const struct clk_hw *[]) {
1494-
&meson8b_vclk2_clk_in_en.hw
1519+
&meson8b_vclk2_clk_en.hw
14951520
},
14961521
.num_parents = 1,
14971522
.flags = CLK_SET_RATE_PARENT,
@@ -2827,6 +2852,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
28272852
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
28282853
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
28292854
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2855+
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
28302856
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
28312857
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
28322858
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
@@ -2838,6 +2864,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
28382864
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
28392865
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
28402866
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2867+
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
28412868
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
28422869
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
28432870
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
@@ -3032,6 +3059,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
30323059
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
30333060
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
30343061
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3062+
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
30353063
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
30363064
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
30373065
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
@@ -3043,6 +3071,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
30433071
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
30443072
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
30453073
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3074+
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
30463075
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
30473076
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
30483077
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
@@ -3248,6 +3277,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
32483277
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
32493278
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
32503279
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3280+
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
32513281
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
32523282
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
32533283
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
@@ -3259,6 +3289,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
32593289
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
32603290
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
32613291
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3292+
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
32623293
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
32633294
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
32643295
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
@@ -3450,13 +3481,15 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
34503481
&meson8b_vid_pll_final_div,
34513482
&meson8b_vclk_in_sel,
34523483
&meson8b_vclk_in_en,
3484+
&meson8b_vclk_en,
34533485
&meson8b_vclk_div1_gate,
34543486
&meson8b_vclk_div2_div_gate,
34553487
&meson8b_vclk_div4_div_gate,
34563488
&meson8b_vclk_div6_div_gate,
34573489
&meson8b_vclk_div12_div_gate,
34583490
&meson8b_vclk2_in_sel,
34593491
&meson8b_vclk2_clk_in_en,
3492+
&meson8b_vclk2_clk_en,
34603493
&meson8b_vclk2_div1_gate,
34613494
&meson8b_vclk2_div2_div_gate,
34623495
&meson8b_vclk2_div4_div_gate,

‎drivers/clk/meson/meson8b.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -180,8 +180,10 @@
180180
#define CLKID_CTS_AMCLK_DIV 208
181181
#define CLKID_CTS_MCLK_I958_SEL 210
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#define CLKID_CTS_MCLK_I958_DIV 211
183+
#define CLKID_VCLK_EN 214
184+
#define CLKID_VCLK2_EN 215
183185

184-
#define CLK_NR_CLKS 214
186+
#define CLK_NR_CLKS 216
185187

186188
/*
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* include the CLKID and RESETID that have

‎include/dt-bindings/clock/g12a-clkc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -145,5 +145,7 @@
145145
#define CLKID_CPU3_CLK 255
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#define CLKID_SPICC0_SCLK 258
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#define CLKID_SPICC1_SCLK 261
148+
#define CLKID_NNA_AXI_CLK 264
149+
#define CLKID_NNA_CORE_CLK 267
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149151
#endif /* __G12A_CLKC_H */

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