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superna9999vinodkoul
superna9999
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phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5
Update the SM8650 UFS PHY init tables to support Gear 4 and Gear 5 using the overlays setup (only supported Gear 5 before), and sync back with the latest Qualcomm recommended values. The new recommended values allow a solid 50% bump in sequential read/write benchmarks on the SM8650 QRD & HDK reference boards. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/20240410-topic-sm8650-upstream-ufs-g5-v1-1-5527c44b37e6@linaro.org Signed-off-by: Vinod Koul <[email protected]>
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+68
-15
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3 files changed

+68
-15
lines changed

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,5 +30,9 @@
3030
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
3131
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
3232
#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
33+
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4 0x240
34+
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5 0x244
35+
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6 0x248
36+
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7 0x24c
3337

3438
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,19 +25,25 @@
2525
#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
2626
#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
2727
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
28+
#define QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0x1ac
2829
#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
2930
#define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0
3031
#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
3132
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
3233
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
34+
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2 0x210
3335
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
36+
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4 0x218
3437
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220
3538
#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238
3639
#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244
3740
#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c
3841
#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260
3942
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
4043
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
44+
#define QSERDES_UFS_V6_RX_MODE_RATE4_B0 0x274
45+
#define QSERDES_UFS_V6_RX_MODE_RATE4_B1 0x278
46+
#define QSERDES_UFS_V6_RX_MODE_RATE4_B2 0x27c
4147
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
4248
#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
4349
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c

‎drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

Lines changed: 58 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -862,59 +862,91 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {
862862
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
863863
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
864864
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
865-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
866-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
865+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
866+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f),
867+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
868+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
869+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
867870
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
868871
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
869-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
872+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
870873
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
871874
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
872875
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
873876
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
874877
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
875-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
878+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
876879
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
877880
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
878881
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
879882
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
880883
};
881884

882885
static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {
883-
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
886+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01),
884887
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
888+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
885889
};
886890

887891
static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {
888892
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
889-
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f),
890-
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
891-
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
892-
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
893+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
894+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
895+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
896+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
897+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
898+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
899+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
900+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
901+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
902+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
903+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
904+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
905+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
893906
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
907+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
894908
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
895909
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
896910
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
897911
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
898912
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
899913
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
900914
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
915+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24),
916+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24),
917+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20),
901918
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
902-
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
919+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
903920
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f),
904921
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
905922
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa),
923+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
906924
};
907925

908926
static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {
909-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x00),
927+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
910928
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
911929
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1),
912-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
930+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
931+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
932+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),
933+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
934+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
935+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
936+
};
937+
938+
static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = {
939+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x13),
913940
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
914941
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
915-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
916-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
917-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
942+
};
943+
944+
static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
945+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
946+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
947+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
948+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
949+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
918950
};
919951

920952
struct qmp_ufs_offsets {
@@ -1475,6 +1507,17 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
14751507
.pcs = sm8650_ufsphy_pcs,
14761508
.pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs),
14771509
},
1510+
.tbls_hs_overlay[0] = {
1511+
.pcs = sm8650_ufsphy_g4_pcs,
1512+
.pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs),
1513+
.max_gear = UFS_HS_G4,
1514+
},
1515+
.tbls_hs_overlay[1] = {
1516+
.pcs = sm8650_ufsphy_g5_pcs,
1517+
.pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
1518+
.max_gear = UFS_HS_G5,
1519+
},
1520+
14781521
.vreg_list = qmp_phy_vreg_l,
14791522
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
14801523
.regs = ufsphy_v6_regs_layout,

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