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Merge tag 'devicetree-fixes-for-5.6-3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring: "Another batch of DT fixes. I think this should be the last of it, but sending pull requests seems to cause people to send more fixes. Summary: - Fixes for warnings introduced by hierarchical PSCI binding changes - Fixes for broken doc references due to DT schema conversions - Several grammar and typo fixes - Fix a bunch of dtc warnings in examples" * tag 'devicetree-fixes-for-5.6-3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: arm: Fixup the DT bindings for hierarchical PSCI states dt-bindings: power: Extend nodename pattern for power-domain providers MAINTAINERS: update ALLWINNER CPUFREQ DRIVER entry dt-bindings: bus: Drop empty compatible string in example dt-bindings: power: Convert domain-idle-states bindings to json-schema dt-bindings: arm: Fix cpu compatibles in the hierarchical example for PSCI dt-bindings: arm: Correct links to idle states definitions dt-bindings: mfd: Fix typo in file name of twl-familly.txt dt-bindings: mfd: tps65910: Improve grammar dt-bindings: mfd: zii,rave-sp: Fix a typo ("onborad") dt-bindings: arm: fsl: fix APF6Dev compatible dt-bindings: Fix dtc warnings in examples docs: dt: fix several broken doc references docs: dt: fix several broken references due to renames MAINTAINERS: clean up PCIE DRIVER FOR CAVIUM THUNDERX
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Documentation/devicetree/bindings/arm/arm,scmi.txt

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@@ -102,7 +102,7 @@ Required sub-node properties:
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power-domain.yaml
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[3] Documentation/devicetree/bindings/thermal/thermal.txt
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[4] Documentation/devicetree/bindings/sram/sram.txt
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[4] Documentation/devicetree/bindings/sram/sram.yaml
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[5] Documentation/devicetree/bindings/reset/reset.txt
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Example:

Documentation/devicetree/bindings/arm/arm,scpi.txt

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[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/thermal/thermal.txt
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[3] Documentation/devicetree/bindings/sram/sram.txt
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[3] Documentation/devicetree/bindings/sram/sram.yaml
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[4] Documentation/devicetree/bindings/power/power-domain.yaml
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Example:

Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt

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Syscon reboot node:
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See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the
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See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the
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detailed list of properties, the two values defined below are specific to the
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BCM6328-style timer:
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Documentation/devicetree/bindings/arm/cpus.yaml

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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description: |
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List of phandles to idle state nodes supported
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by this cpu (see ./idle-states.txt).
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by this cpu (see ./idle-states.yaml).
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capacity-dmips-mhz:
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$ref: '/schemas/types.yaml#/definitions/uint32'

Documentation/devicetree/bindings/arm/fsl.yaml

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items:
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- enum:
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- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
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- armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board
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- armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board
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- eckelmann,imx6dl-ci4x10
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- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
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- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base

Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt

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* Hisilicon Hi3519 System Controller Block
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This bindings use the following binding:
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Documentation/devicetree/bindings/mfd/syscon.txt
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Documentation/devicetree/bindings/mfd/syscon.yaml
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Required properties:
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- compatible: "hisilicon,hi3519-sysctrl".

Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt

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};
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};
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[1]. Documentation/devicetree/bindings/arm/idle-states.txt
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[1]. Documentation/devicetree/bindings/arm/idle-states.yaml

Documentation/devicetree/bindings/arm/omap/mpu.txt

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- pm-sram: Phandles to ocmcram nodes to be used for power management.
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First should be type 'protect-exec' for the driver to use to copy
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and run PM functions, second should be regular pool to be used for
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data region for code. See Documentation/devicetree/bindings/sram/sram.txt
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data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
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for more details.
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Examples:

Documentation/devicetree/bindings/arm/psci.yaml

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bindings in [1]) must specify this property.
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[1] Kernel documentation - ARM idle states bindings
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Documentation/devicetree/bindings/arm/idle-states.txt
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"#power-domain-cells":
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description:
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The number of cells in a PM domain specifier as per binding in [3].
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Must be 0 as to represent a single PM domain.
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Documentation/devicetree/bindings/arm/idle-states.yaml
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patternProperties:
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"^power-domain-":
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allOf:
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- $ref: "../power/power-domain.yaml#"
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type: object
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description: |
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ARM systems can have multiple cores, sometimes in an hierarchical
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arrangement. This often, but not always, maps directly to the processor
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power topology of the system. Individual nodes in a topology have their
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helps to implement support for OSI mode and OS implementations may choose
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to mandate it.
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[3] Documentation/devicetree/bindings/power/power_domain.txt
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[4] Documentation/devicetree/bindings/power/domain-idle-state.txt
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power-domains:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description:
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List of phandles and PM domain specifiers, as defined by bindings of the
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PM domain provider.
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[3] Documentation/devicetree/bindings/power/power-domain.yaml
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[4] Documentation/devicetree/bindings/power/domain-idle-state.yaml
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required:
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- compatible
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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power-domains = <&CPU_PD0>;
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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power-domains = <&CPU_PD1>;
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exit-latency-us = <10>;
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min-residency-us = <100>;
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};
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};
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domain-idle-states {
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CLUSTER_RET: cluster-retention {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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CPU_PD0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CPU_PWRDN>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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CPU_PD1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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domain-idle-states = <&CPU_PWRDN>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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CLUSTER_PD: power-domain-cluster {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
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};

Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml

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examples:
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- |
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mlahb: ahb {
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mlahb: ahb@38000000 {
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compatible = "st,mlahb", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;

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