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Merge branch 'for-v6.12/clk-dt-bindings' into next/clk
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‎Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung ExynosAuto v920 SoC clock controller
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maintainers:
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- Sunyeal Hong <[email protected]>
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- Chanwoo Choi <[email protected]>
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- Krzysztof Kozlowski <[email protected]>
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- Sylwester Nawrocki <[email protected]>
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description: |
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ExynosAuto v920 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. Root clocks in that clock tree are
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two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
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The external OSCCLK must be defined as fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/samsung,exynosautov920.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynosautov920-cmu-top
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
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- samsung,exynosautov920-cmu-misc
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- samsung,exynosautov920-cmu-hsi0
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- samsung,exynosautov920-cmu-hsi1
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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clock-names:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_PERICn NOC clock (from CMU_TOP)
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- description: CMU_PERICn IP clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- const: ip
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- if:
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properties:
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compatible:
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enum:
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- samsung,exynosautov920-cmu-misc
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- samsung,exynosautov920-cmu-hsi0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-hsi1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_HSI1 NOC clock (from CMU_TOP)
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- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
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- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- const: usbdrd
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- const: mmc_card
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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- reg
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additionalProperties: false
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examples:
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# Clock controller node for CMU_PERIC0
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- |
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#include <dt-bindings/clock/samsung,exynosautov920.h>
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cmu_peric0: clock-controller@10800000 {
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compatible = "samsung,exynosautov920-cmu-peric0";
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reg = <0x10800000 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
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<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
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clock-names = "oscclk",
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"noc",
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"ip";
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};
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...

‎include/dt-bindings/clock/samsung,exynosautov920.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024 Samsung Electronics Co., Ltd.
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* Author: Sunyeal Hong <[email protected]>
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*
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* Device Tree binding constants for ExynosAuto v920 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
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#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
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/* CMU_TOP */
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#define FOUT_SHARED0_PLL 1
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#define FOUT_SHARED1_PLL 2
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#define FOUT_SHARED2_PLL 3
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#define FOUT_SHARED3_PLL 4
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#define FOUT_SHARED4_PLL 5
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#define FOUT_SHARED5_PLL 6
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#define FOUT_MMC_PLL 7
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/* MUX in CMU_TOP */
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#define MOUT_SHARED0_PLL 8
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#define MOUT_SHARED1_PLL 9
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#define MOUT_SHARED2_PLL 10
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#define MOUT_SHARED3_PLL 11
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#define MOUT_SHARED4_PLL 12
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#define MOUT_SHARED5_PLL 13
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#define MOUT_MMC_PLL 14
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#define MOUT_CLKCMU_CMU_BOOST 15
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#define MOUT_CLKCMU_CMU_CMUREF 16
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#define MOUT_CLKCMU_ACC_NOC 17
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#define MOUT_CLKCMU_ACC_ORB 18
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#define MOUT_CLKCMU_APM_NOC 19
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#define MOUT_CLKCMU_AUD_CPU 20
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#define MOUT_CLKCMU_AUD_NOC 21
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#define MOUT_CLKCMU_CPUCL0_SWITCH 22
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#define MOUT_CLKCMU_CPUCL0_CLUSTER 23
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#define MOUT_CLKCMU_CPUCL0_DBG 24
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#define MOUT_CLKCMU_CPUCL1_SWITCH 25
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#define MOUT_CLKCMU_CPUCL1_CLUSTER 26
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#define MOUT_CLKCMU_CPUCL2_SWITCH 27
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#define MOUT_CLKCMU_CPUCL2_CLUSTER 28
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#define MOUT_CLKCMU_DNC_NOC 29
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#define MOUT_CLKCMU_DPTX_NOC 30
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#define MOUT_CLKCMU_DPTX_DPGTC 31
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#define MOUT_CLKCMU_DPTX_DPOSC 32
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#define MOUT_CLKCMU_DPUB_NOC 33
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#define MOUT_CLKCMU_DPUB_DSIM 34
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#define MOUT_CLKCMU_DPUF0_NOC 35
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#define MOUT_CLKCMU_DPUF1_NOC 36
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#define MOUT_CLKCMU_DPUF2_NOC 37
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#define MOUT_CLKCMU_DSP_NOC 38
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#define MOUT_CLKCMU_G3D_SWITCH 39
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#define MOUT_CLKCMU_G3D_NOCP 40
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#define MOUT_CLKCMU_GNPU_NOC 41
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#define MOUT_CLKCMU_HSI0_NOC 42
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#define MOUT_CLKCMU_HSI1_NOC 43
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#define MOUT_CLKCMU_HSI1_USBDRD 44
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#define MOUT_CLKCMU_HSI1_MMC_CARD 45
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#define MOUT_CLKCMU_HSI2_NOC 46
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#define MOUT_CLKCMU_HSI2_NOC_UFS 47
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#define MOUT_CLKCMU_HSI2_UFS_EMBD 48
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#define MOUT_CLKCMU_HSI2_ETHERNET 49
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#define MOUT_CLKCMU_ISP_NOC 50
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#define MOUT_CLKCMU_M2M_NOC 51
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#define MOUT_CLKCMU_M2M_JPEG 52
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#define MOUT_CLKCMU_MFC_MFC 53
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#define MOUT_CLKCMU_MFC_WFD 54
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#define MOUT_CLKCMU_MFD_NOC 55
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#define MOUT_CLKCMU_MIF_SWITCH 56
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#define MOUT_CLKCMU_MIF_NOCP 57
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#define MOUT_CLKCMU_MISC_NOC 58
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#define MOUT_CLKCMU_NOCL0_NOC 59
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#define MOUT_CLKCMU_NOCL1_NOC 60
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#define MOUT_CLKCMU_NOCL2_NOC 61
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#define MOUT_CLKCMU_PERIC0_NOC 62
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#define MOUT_CLKCMU_PERIC0_IP 63
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#define MOUT_CLKCMU_PERIC1_NOC 64
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#define MOUT_CLKCMU_PERIC1_IP 65
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#define MOUT_CLKCMU_SDMA_NOC 66
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#define MOUT_CLKCMU_SNW_NOC 67
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#define MOUT_CLKCMU_SSP_NOC 68
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#define MOUT_CLKCMU_TAA_NOC 69
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/* DIV in CMU_TOP */
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#define DOUT_SHARED0_DIV1 70
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#define DOUT_SHARED0_DIV2 71
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#define DOUT_SHARED0_DIV3 72
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#define DOUT_SHARED0_DIV4 73
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#define DOUT_SHARED1_DIV1 74
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#define DOUT_SHARED1_DIV2 75
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#define DOUT_SHARED1_DIV3 76
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#define DOUT_SHARED1_DIV4 77
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#define DOUT_SHARED2_DIV1 78
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#define DOUT_SHARED2_DIV2 79
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#define DOUT_SHARED2_DIV3 80
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#define DOUT_SHARED2_DIV4 81
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#define DOUT_SHARED3_DIV1 82
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#define DOUT_SHARED3_DIV2 83
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#define DOUT_SHARED3_DIV3 84
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#define DOUT_SHARED3_DIV4 85
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#define DOUT_SHARED4_DIV1 86
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#define DOUT_SHARED4_DIV2 87
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#define DOUT_SHARED4_DIV3 88
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#define DOUT_SHARED4_DIV4 89
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#define DOUT_SHARED5_DIV1 90
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#define DOUT_SHARED5_DIV2 91
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#define DOUT_SHARED5_DIV3 92
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#define DOUT_SHARED5_DIV4 93
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#define DOUT_CLKCMU_CMU_BOOST 94
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#define DOUT_CLKCMU_ACC_NOC 95
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#define DOUT_CLKCMU_ACC_ORB 96
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#define DOUT_CLKCMU_APM_NOC 97
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#define DOUT_CLKCMU_AUD_CPU 98
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#define DOUT_CLKCMU_AUD_NOC 99
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#define DOUT_CLKCMU_CPUCL0_SWITCH 100
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#define DOUT_CLKCMU_CPUCL0_CLUSTER 101
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#define DOUT_CLKCMU_CPUCL0_DBG 102
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#define DOUT_CLKCMU_CPUCL1_SWITCH 103
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#define DOUT_CLKCMU_CPUCL1_CLUSTER 104
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#define DOUT_CLKCMU_CPUCL2_SWITCH 105
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#define DOUT_CLKCMU_CPUCL2_CLUSTER 106
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#define DOUT_CLKCMU_DNC_NOC 107
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#define DOUT_CLKCMU_DPTX_NOC 108
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#define DOUT_CLKCMU_DPTX_DPGTC 109
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#define DOUT_CLKCMU_DPTX_DPOSC 110
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#define DOUT_CLKCMU_DPUB_NOC 111
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#define DOUT_CLKCMU_DPUB_DSIM 112
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#define DOUT_CLKCMU_DPUF0_NOC 113
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#define DOUT_CLKCMU_DPUF1_NOC 114
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#define DOUT_CLKCMU_DPUF2_NOC 115
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#define DOUT_CLKCMU_DSP_NOC 116
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#define DOUT_CLKCMU_G3D_SWITCH 117
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#define DOUT_CLKCMU_G3D_NOCP 118
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#define DOUT_CLKCMU_GNPU_NOC 119
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#define DOUT_CLKCMU_HSI0_NOC 120
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#define DOUT_CLKCMU_HSI1_NOC 121
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#define DOUT_CLKCMU_HSI1_USBDRD 122
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#define DOUT_CLKCMU_HSI1_MMC_CARD 123
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#define DOUT_CLKCMU_HSI2_NOC 124
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#define DOUT_CLKCMU_HSI2_NOC_UFS 125
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#define DOUT_CLKCMU_HSI2_UFS_EMBD 126
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#define DOUT_CLKCMU_HSI2_ETHERNET 127
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#define DOUT_CLKCMU_ISP_NOC 128
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#define DOUT_CLKCMU_M2M_NOC 129
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#define DOUT_CLKCMU_M2M_JPEG 130
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#define DOUT_CLKCMU_MFC_MFC 131
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#define DOUT_CLKCMU_MFC_WFD 132
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#define DOUT_CLKCMU_MFD_NOC 133
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#define DOUT_CLKCMU_MIF_NOCP 134
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#define DOUT_CLKCMU_MISC_NOC 135
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#define DOUT_CLKCMU_NOCL0_NOC 136
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#define DOUT_CLKCMU_NOCL1_NOC 137
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#define DOUT_CLKCMU_NOCL2_NOC 138
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#define DOUT_CLKCMU_PERIC0_NOC 139
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#define DOUT_CLKCMU_PERIC0_IP 140
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#define DOUT_CLKCMU_PERIC1_NOC 141
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#define DOUT_CLKCMU_PERIC1_IP 142
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#define DOUT_CLKCMU_SDMA_NOC 143
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#define DOUT_CLKCMU_SNW_NOC 144
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#define DOUT_CLKCMU_SSP_NOC 145
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#define DOUT_CLKCMU_TAA_NOC 146
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/* CMU_PERIC0 */
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#define CLK_MOUT_PERIC0_IP_USER 1
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#define CLK_MOUT_PERIC0_NOC_USER 2
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#define CLK_MOUT_PERIC0_USI00_USI 3
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#define CLK_MOUT_PERIC0_USI01_USI 4
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#define CLK_MOUT_PERIC0_USI02_USI 5
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#define CLK_MOUT_PERIC0_USI03_USI 6
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#define CLK_MOUT_PERIC0_USI04_USI 7
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#define CLK_MOUT_PERIC0_USI05_USI 8
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#define CLK_MOUT_PERIC0_USI06_USI 9
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#define CLK_MOUT_PERIC0_USI07_USI 10
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#define CLK_MOUT_PERIC0_USI08_USI 11
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#define CLK_MOUT_PERIC0_USI_I2C 12
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#define CLK_MOUT_PERIC0_I3C 13
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#define CLK_DOUT_PERIC0_USI00_USI 14
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#define CLK_DOUT_PERIC0_USI01_USI 15
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#define CLK_DOUT_PERIC0_USI02_USI 16
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#define CLK_DOUT_PERIC0_USI03_USI 17
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#define CLK_DOUT_PERIC0_USI04_USI 18
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#define CLK_DOUT_PERIC0_USI05_USI 19
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#define CLK_DOUT_PERIC0_USI06_USI 20
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#define CLK_DOUT_PERIC0_USI07_USI 21
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#define CLK_DOUT_PERIC0_USI08_USI 22
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#define CLK_DOUT_PERIC0_USI_I2C 23
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#define CLK_DOUT_PERIC0_I3C 24
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#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */

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