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Merge tag 'juno-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/FVP updates for v6.16 Few updates to the Arm FVP(Fixed Virtual Platform) device tree, enhancing support for system tracing, power management, and firmware coexistence: 1. ETE and TRBE support Adds CoreSight ETE and TRBE nodes for the FVP Rev C model. These are disabled by default as they need to be enabled explicitly via model parameters. 2. CPU idle states and system timer for idle broadcast Introduces CPU idle state definitions but disabled by default due to potential performance impact on the model. Also adds a system-level broadcast timer for use when CPUs enter deep idle states where local timers stop. 3. Firmware memory reservation Reserves 64MB at the end of the first DRAM bank to prevent conflicts with FF-A firmware or similar configurations that rely on this region. 4. Drop the unnecessary clock-frequency property in the timer nodes The boot/secure firmware must configure the timer clock frequency and the non-secure OS must be able to read the same. The clock-frequency is generally used when the firmware is broken which is not the case on most of the fast models and Juno platform. As noted above some of the changes are disabled by default where applicable to ensure backward compatibility and avoid unintended performance impact on platforms using default model parameters. * tag 'juno-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model arm64: dts: arm: Drop the clock-frequency property from timer nodes arm64: dts: fvp: Reserve 64MB for the FF-A firmware in memory map arm64: dts: fvp: Add CPU idle states for Rev C model arm64: dts: fvp: Add system timer for broadcast during CPU idle Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents b5125e6 + 6332351 commit c48cd2e

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‎arch/arm64/boot/dts/arm/corstone1000.dtsi

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@@ -109,7 +109,6 @@
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reg = <0x1a220000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-frequency = <50000000>;
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ranges;
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frame@1a230000 {

‎arch/arm64/boot/dts/arm/foundation-v8.dtsi

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@@ -77,7 +77,6 @@
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <100000000>;
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};
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pmu {

‎arch/arm64/boot/dts/arm/fvp-base-revc.dts

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@@ -44,6 +44,30 @@
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#address-cells = <2>;
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#size-cells = <0>;
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <150>;
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status = "disabled";
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <500>;
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exit-latency-us = <1000>;
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min-residency-us = <2500>;
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status = "disabled";
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
@@ -56,6 +80,7 @@
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C0_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C0_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C0_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C0_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu4: cpu@10000 {
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device_type = "cpu";
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C1_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu5: cpu@10100 {
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device_type = "cpu";
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C1_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu6: cpu@10200 {
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device_type = "cpu";
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C1_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu7: cpu@10300 {
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device_type = "cpu";
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&C1_L2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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C0_L2: l2-cache0 {
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compatible = "cache";
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>,
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reg = <0x00000000 0x80000000 0 0x7c000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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};
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@@ -217,6 +249,19 @@
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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ranges = <0 0x0 0x2a820000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x10000 0x10000>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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ete-0 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu0>;
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status = "disabled";
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};
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ete-1 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu1>;
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status = "disabled";
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};
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ete-2 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu2>;
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status = "disabled";
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};
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ete-3 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu3>;
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status = "disabled";
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};
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ete-4 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu4>;
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status = "disabled";
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};
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ete-5 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu5>;
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status = "disabled";
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};
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ete-6 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu6>;
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status = "disabled";
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};
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ete-7 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&cpu7>;
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status = "disabled";
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};
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trbe {
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compatible = "arm,trace-buffer-extension";
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_LOW>;
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status = "disabled";
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};
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pci: pci@40000000 {
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#address-cells = <0x3>;
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#size-cells = <0x2>;

‎arch/arm64/boot/dts/arm/juno-base.dtsi

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@@ -10,7 +10,6 @@
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memtimer: timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x2a820000 0x20000>;

‎arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts

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@@ -116,7 +116,6 @@
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <100000000>;
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};
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pmu {

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