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Marek Olšákalexdeucher
Marek Olšák
authored and
alexdeucher
committed
drm/amdgpu: apply AMDGPU_IB_FLAG_EMIT_MEM_SYNC to compute IBs too (v3)
Compute IBs need this too. v2: split out version bump v3: squash in emit frame count fixes Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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7 files changed

+46
-7
lines changed

7 files changed

+46
-7
lines changed

‎drivers/gpu/drm/amd/amdgpu/cikd.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -450,7 +450,7 @@
450450
# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
451451
# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
452452
# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
453-
#define PACKET3_AQUIRE_MEM 0x58
453+
#define PACKET3_ACQUIRE_MEM 0x58
454454
#define PACKET3_REWIND 0x59
455455
#define PACKET3_LOAD_UCONFIG_REG 0x5E
456456
#define PACKET3_LOAD_SH_REG 0x5F

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8133,7 +8133,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
81338133
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
81348134
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
81358135
2 + /* gfx_v10_0_ring_emit_vm_flush */
8136-
8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8136+
8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8137+
8, /* gfx_v10_0_emit_mem_sync */
81378138
.emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
81388139
.emit_ib = gfx_v10_0_ring_emit_ib_compute,
81398140
.emit_fence = gfx_v10_0_ring_emit_fence,
@@ -8148,6 +8149,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
81488149
.emit_wreg = gfx_v10_0_ring_emit_wreg,
81498150
.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
81508151
.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8152+
.emit_mem_sync = gfx_v10_0_emit_mem_sync,
81518153
};
81528154

81538155
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3533,7 +3533,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
35333533
5 + 5 + /* hdp flush / invalidate */
35343534
7 + /* gfx_v6_0_ring_emit_pipeline_sync */
35353535
SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3536-
14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3536+
14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3537+
5, /* SURFACE_SYNC */
35373538
.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
35383539
.emit_ib = gfx_v6_0_ring_emit_ib,
35393540
.emit_fence = gfx_v6_0_ring_emit_fence,
@@ -3543,6 +3544,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
35433544
.test_ib = gfx_v6_0_ring_test_ib,
35443545
.insert_nop = amdgpu_ring_insert_nop,
35453546
.emit_wreg = gfx_v6_0_ring_emit_wreg,
3547+
.emit_mem_sync = gfx_v6_0_emit_mem_sync,
35463548
};
35473549

35483550
static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5010,6 +5010,20 @@ static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring)
50105010
amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
50115011
}
50125012

5013+
static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
5014+
{
5015+
amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
5016+
amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
5017+
PACKET3_TC_ACTION_ENA |
5018+
PACKET3_SH_KCACHE_ACTION_ENA |
5019+
PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */
5020+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
5021+
amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */
5022+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
5023+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
5024+
amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
5025+
}
5026+
50135027
static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
50145028
.name = "gfx_v7_0",
50155029
.early_init = gfx_v7_0_early_init,
@@ -5075,7 +5089,8 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
50755089
5 + /* hdp invalidate */
50765090
7 + /* gfx_v7_0_ring_emit_pipeline_sync */
50775091
CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
5078-
7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5092+
7 + 7 + 7 + /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5093+
7, /* gfx_v7_0_emit_mem_sync_compute */
50795094
.emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */
50805095
.emit_ib = gfx_v7_0_ring_emit_ib_compute,
50815096
.emit_fence = gfx_v7_0_ring_emit_fence_compute,
@@ -5088,6 +5103,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
50885103
.insert_nop = amdgpu_ring_insert_nop,
50895104
.pad_ib = amdgpu_ring_generic_pad_ib,
50905105
.emit_wreg = gfx_v7_0_ring_emit_wreg,
5106+
.emit_mem_sync = gfx_v7_0_emit_mem_sync_compute,
50915107
};
50925108

50935109
static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6830,6 +6830,21 @@ static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring)
68306830
amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
68316831
}
68326832

6833+
static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
6834+
{
6835+
amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6836+
amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6837+
PACKET3_TC_ACTION_ENA |
6838+
PACKET3_SH_KCACHE_ACTION_ENA |
6839+
PACKET3_SH_ICACHE_ACTION_ENA |
6840+
PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6841+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6842+
amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */
6843+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6844+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6845+
amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6846+
}
6847+
68336848
static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
68346849
.name = "gfx_v8_0",
68356850
.early_init = gfx_v8_0_early_init,
@@ -6912,7 +6927,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
69126927
5 + /* hdp_invalidate */
69136928
7 + /* gfx_v8_0_ring_emit_pipeline_sync */
69146929
VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6915-
7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6930+
7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6931+
7, /* gfx_v8_0_emit_mem_sync_compute */
69166932
.emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
69176933
.emit_ib = gfx_v8_0_ring_emit_ib_compute,
69186934
.emit_fence = gfx_v8_0_ring_emit_fence_compute,
@@ -6925,6 +6941,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
69256941
.insert_nop = amdgpu_ring_insert_nop,
69266942
.pad_ib = amdgpu_ring_generic_pad_ib,
69276943
.emit_wreg = gfx_v8_0_ring_emit_wreg,
6944+
.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
69286945
};
69296946

69306947
static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6741,7 +6741,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
67416741
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
67426742
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
67436743
2 + /* gfx_v9_0_ring_emit_vm_flush */
6744-
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
6744+
8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
6745+
7, /* gfx_v9_0_emit_mem_sync */
67456746
.emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
67466747
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
67476748
.emit_fence = gfx_v9_0_ring_emit_fence,
@@ -6756,6 +6757,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
67566757
.emit_wreg = gfx_v9_0_ring_emit_wreg,
67576758
.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
67586759
.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6760+
.emit_mem_sync = gfx_v9_0_emit_mem_sync,
67596761
};
67606762

67616763
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {

‎drivers/gpu/drm/amd/amdgpu/vid.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -332,7 +332,7 @@
332332
# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
333333
# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
334334
# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
335-
#define PACKET3_AQUIRE_MEM 0x58
335+
#define PACKET3_ACQUIRE_MEM 0x58
336336
#define PACKET3_REWIND 0x59
337337
#define PACKET3_LOAD_UCONFIG_REG 0x5E
338338
#define PACKET3_LOAD_SH_REG 0x5F

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