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Ping-Ke ShihKalle Valo
Ping-Ke Shih
authored and
Kalle Valo
committed
wifi: rtw89: 8922ae: add v2 interrupt handlers for 8922AE
The handlers include three parts -- 1) configure interrupt mask; 2) enable/disable interrupt; 3) recognize (read) interrupt status. Signed-off-by: Ping-Ke Shih <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎drivers/net/wireless/realtek/rtw89/pci.c

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -696,6 +696,27 @@ void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
696696
}
697697
EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v1);
698698

699+
void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev,
700+
struct rtw89_pci *rtwpci,
701+
struct rtw89_pci_isrs *isrs)
702+
{
703+
isrs->ind_isrs = rtw89_read32(rtwdev, R_BE_PCIE_HISR) & rtwpci->ind_intrs;
704+
isrs->halt_c2h_isrs = isrs->ind_isrs & B_BE_HS0ISR_IND_INT ?
705+
rtw89_read32(rtwdev, R_BE_HISR0) & rtwpci->halt_c2h_intrs : 0;
706+
isrs->isrs[0] = isrs->ind_isrs & B_BE_HCI_AXIDMA_INT ?
707+
rtw89_read32(rtwdev, R_BE_HAXI_HISR00) & rtwpci->intrs[0] : 0;
708+
isrs->isrs[1] = rtw89_read32(rtwdev, R_BE_PCIE_DMA_ISR);
709+
710+
if (isrs->halt_c2h_isrs)
711+
rtw89_write32(rtwdev, R_BE_HISR0, isrs->halt_c2h_isrs);
712+
if (isrs->isrs[0])
713+
rtw89_write32(rtwdev, R_BE_HAXI_HISR00, isrs->isrs[0]);
714+
if (isrs->isrs[1])
715+
rtw89_write32(rtwdev, R_BE_PCIE_DMA_ISR, isrs->isrs[1]);
716+
rtw89_write32(rtwdev, R_BE_PCIE_HISR, isrs->ind_isrs);
717+
}
718+
EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v2);
719+
699720
void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
700721
{
701722
rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
@@ -727,6 +748,22 @@ void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpc
727748
}
728749
EXPORT_SYMBOL(rtw89_pci_disable_intr_v1);
729750

751+
void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
752+
{
753+
rtw89_write32(rtwdev, R_BE_HIMR0, rtwpci->halt_c2h_intrs);
754+
rtw89_write32(rtwdev, R_BE_HAXI_HIMR00, rtwpci->intrs[0]);
755+
rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, rtwpci->intrs[1]);
756+
rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, rtwpci->ind_intrs);
757+
}
758+
EXPORT_SYMBOL(rtw89_pci_enable_intr_v2);
759+
760+
void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
761+
{
762+
rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, 0);
763+
rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, 0);
764+
}
765+
EXPORT_SYMBOL(rtw89_pci_disable_intr_v2);
766+
730767
static void rtw89_pci_ops_recovery_start(struct rtw89_dev *rtwdev)
731768
{
732769
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
@@ -3343,6 +3380,55 @@ void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev)
33433380
}
33443381
EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v1);
33453382

3383+
static void rtw89_pci_recovery_intr_mask_v2(struct rtw89_dev *rtwdev)
3384+
{
3385+
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3386+
3387+
rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0;
3388+
rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3389+
rtwpci->intrs[0] = 0;
3390+
rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 |
3391+
B_BE_PCIE_RX_RPQ0_IMR0_V1;
3392+
}
3393+
3394+
static void rtw89_pci_default_intr_mask_v2(struct rtw89_dev *rtwdev)
3395+
{
3396+
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3397+
3398+
rtwpci->ind_intrs = B_BE_HCI_AXIDMA_INT_EN0 |
3399+
B_BE_HS0_IND_INT_EN0;
3400+
rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3401+
rtwpci->intrs[0] = B_BE_RDU_CH1_INT_IMR_V1 |
3402+
B_BE_RDU_CH0_INT_IMR_V1;
3403+
rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 |
3404+
B_BE_PCIE_RX_RPQ0_IMR0_V1;
3405+
}
3406+
3407+
static void rtw89_pci_low_power_intr_mask_v2(struct rtw89_dev *rtwdev)
3408+
{
3409+
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3410+
3411+
rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0 |
3412+
B_BE_HS1_IND_INT_EN0;
3413+
rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3414+
rtwpci->intrs[0] = 0;
3415+
rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 |
3416+
B_BE_PCIE_RX_RPQ0_IMR0_V1;
3417+
}
3418+
3419+
void rtw89_pci_config_intr_mask_v2(struct rtw89_dev *rtwdev)
3420+
{
3421+
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3422+
3423+
if (rtwpci->under_recovery)
3424+
rtw89_pci_recovery_intr_mask_v2(rtwdev);
3425+
else if (rtwpci->low_power)
3426+
rtw89_pci_low_power_intr_mask_v2(rtwdev);
3427+
else
3428+
rtw89_pci_default_intr_mask_v2(rtwdev);
3429+
}
3430+
EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v2);
3431+
33463432
static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev,
33473433
struct pci_dev *pdev)
33483434
{

‎drivers/net/wireless/realtek/rtw89/pci.h

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,69 @@
290290
#define B_BE_RTK_LDO_BIAS_LATENCY_MASK GENMASK(9, 8)
291291
#define B_BE_CLK_REQ_LAT_MASK GENMASK(7, 4)
292292

293+
#define R_BE_PCIE_HIMR0 0x30B0
294+
#define B_BE_PCIE_HB1_IND_INTA_IMR BIT(31)
295+
#define B_BE_PCIE_HB0_IND_INTA_IMR BIT(30)
296+
#define B_BE_HCI_AXIDMA_INTA_IMR BIT(29)
297+
#define B_BE_HC0_IND_INTA_IMR BIT(28)
298+
#define B_BE_HD1_IND_INTA_IMR BIT(27)
299+
#define B_BE_HD0_IND_INTA_IMR BIT(26)
300+
#define B_BE_HS1_IND_INTA_IMR BIT(25)
301+
#define B_BE_HS0_IND_INTA_IMR BIT(24)
302+
#define B_BE_PCIE_HOTRST_INT_EN BIT(16)
303+
#define B_BE_PCIE_FLR_INT_EN BIT(15)
304+
#define B_BE_PCIE_PERST_INT_EN BIT(14)
305+
#define B_BE_PCIE_DBG_STE_INT_EN BIT(13)
306+
#define B_BE_HB1_IND_INT_EN0 BIT(9)
307+
#define B_BE_HB0_IND_INT_EN0 BIT(8)
308+
#define B_BE_HC1_IND_INT_EN0 BIT(7)
309+
#define B_BE_HCI_AXIDMA_INT_EN0 BIT(5)
310+
#define B_BE_HC0_IND_INT_EN0 BIT(4)
311+
#define B_BE_HD1_IND_INT_EN0 BIT(3)
312+
#define B_BE_HD0_IND_INT_EN0 BIT(2)
313+
#define B_BE_HS1_IND_INT_EN0 BIT(1)
314+
#define B_BE_HS0_IND_INT_EN0 BIT(0)
315+
316+
#define R_BE_PCIE_HISR 0x30B4
317+
#define B_BE_PCIE_HOTRST_INT BIT(16)
318+
#define B_BE_PCIE_FLR_INT BIT(15)
319+
#define B_BE_PCIE_PERST_INT BIT(14)
320+
#define B_BE_PCIE_DBG_STE_INT BIT(13)
321+
#define B_BE_HB1IMR_IND BIT(9)
322+
#define B_BE_HB0IMR_IND BIT(8)
323+
#define B_BE_HC1ISR_IND_INT BIT(7)
324+
#define B_BE_HCI_AXIDMA_INT BIT(5)
325+
#define B_BE_HC0ISR_IND_INT BIT(4)
326+
#define B_BE_HD1ISR_IND_INT BIT(3)
327+
#define B_BE_HD0ISR_IND_INT BIT(2)
328+
#define B_BE_HS1ISR_IND_INT BIT(1)
329+
#define B_BE_HS0ISR_IND_INT BIT(0)
330+
331+
#define R_BE_PCIE_DMA_IMR_0_V1 0x30B8
332+
#define B_BE_PCIE_RX_RX1P1_IMR0_V1 BIT(23)
333+
#define B_BE_PCIE_RX_RX0P1_IMR0_V1 BIT(22)
334+
#define B_BE_PCIE_RX_ROQ1_IMR0_V1 BIT(21)
335+
#define B_BE_PCIE_RX_RPQ1_IMR0_V1 BIT(20)
336+
#define B_BE_PCIE_RX_RX1P2_IMR0_V1 BIT(19)
337+
#define B_BE_PCIE_RX_ROQ0_IMR0_V1 BIT(18)
338+
#define B_BE_PCIE_RX_RPQ0_IMR0_V1 BIT(17)
339+
#define B_BE_PCIE_RX_RX0P2_IMR0_V1 BIT(16)
340+
#define B_BE_PCIE_TX_CH14_IMR0 BIT(14)
341+
#define B_BE_PCIE_TX_CH13_IMR0 BIT(13)
342+
#define B_BE_PCIE_TX_CH12_IMR0 BIT(12)
343+
#define B_BE_PCIE_TX_CH11_IMR0 BIT(11)
344+
#define B_BE_PCIE_TX_CH10_IMR0 BIT(10)
345+
#define B_BE_PCIE_TX_CH9_IMR0 BIT(9)
346+
#define B_BE_PCIE_TX_CH8_IMR0 BIT(8)
347+
#define B_BE_PCIE_TX_CH7_IMR0 BIT(7)
348+
#define B_BE_PCIE_TX_CH6_IMR0 BIT(6)
349+
#define B_BE_PCIE_TX_CH5_IMR0 BIT(5)
350+
#define B_BE_PCIE_TX_CH4_IMR0 BIT(4)
351+
#define B_BE_PCIE_TX_CH3_IMR0 BIT(3)
352+
#define B_BE_PCIE_TX_CH2_IMR0 BIT(2)
353+
#define B_BE_PCIE_TX_CH1_IMR0 BIT(1)
354+
#define B_BE_PCIE_TX_CH0_IMR0 BIT(0)
355+
293356
#define R_BE_PCIE_DMA_ISR 0x30BC
294357
#define B_BE_PCIE_RX_RX1P1_ISR_V1 BIT(23)
295358
#define B_BE_PCIE_RX_RX0P1_ISR_V1 BIT(22)
@@ -315,6 +378,39 @@
315378
#define B_BE_PCIE_TX_CH1_ISR BIT(1)
316379
#define B_BE_PCIE_TX_CH0_ISR BIT(0)
317380

381+
#define R_BE_HAXI_HIMR00 0xB0B0
382+
#define B_BE_RDU_CH5_INT_IMR_V1 BIT(30)
383+
#define B_BE_RDU_CH4_INT_IMR_V1 BIT(29)
384+
#define B_BE_RDU_CH3_INT_IMR_V1 BIT(28)
385+
#define B_BE_RDU_CH2_INT_IMR_V1 BIT(27)
386+
#define B_BE_RDU_CH1_INT_IMR_V1 BIT(26)
387+
#define B_BE_RDU_CH0_INT_IMR_V1 BIT(25)
388+
#define B_BE_RXDMA_STUCK_INT_EN_V1 BIT(24)
389+
#define B_BE_TXDMA_STUCK_INT_EN_V1 BIT(23)
390+
#define B_BE_TXDMA_CH14_INT_EN_V1 BIT(22)
391+
#define B_BE_TXDMA_CH13_INT_EN_V1 BIT(21)
392+
#define B_BE_TXDMA_CH12_INT_EN_V1 BIT(20)
393+
#define B_BE_TXDMA_CH11_INT_EN_V1 BIT(19)
394+
#define B_BE_TXDMA_CH10_INT_EN_V1 BIT(18)
395+
#define B_BE_TXDMA_CH9_INT_EN_V1 BIT(17)
396+
#define B_BE_TXDMA_CH8_INT_EN_V1 BIT(16)
397+
#define B_BE_TXDMA_CH7_INT_EN_V1 BIT(15)
398+
#define B_BE_TXDMA_CH6_INT_EN_V1 BIT(14)
399+
#define B_BE_TXDMA_CH5_INT_EN_V1 BIT(13)
400+
#define B_BE_TXDMA_CH4_INT_EN_V1 BIT(12)
401+
#define B_BE_TXDMA_CH3_INT_EN_V1 BIT(11)
402+
#define B_BE_TXDMA_CH2_INT_EN_V1 BIT(10)
403+
#define B_BE_TXDMA_CH1_INT_EN_V1 BIT(9)
404+
#define B_BE_TXDMA_CH0_INT_EN_V1 BIT(8)
405+
#define B_BE_RX1P1DMA_INT_EN_V1 BIT(7)
406+
#define B_BE_RX0P1DMA_INT_EN_V1 BIT(6)
407+
#define B_BE_RO1DMA_INT_EN BIT(5)
408+
#define B_BE_RP1DMA_INT_EN BIT(4)
409+
#define B_BE_RX1DMA_INT_EN BIT(3)
410+
#define B_BE_RO0DMA_INT_EN BIT(2)
411+
#define B_BE_RP0DMA_INT_EN BIT(1)
412+
#define B_BE_RX0DMA_INT_EN BIT(0)
413+
318414
#define R_BE_HAXI_HISR00 0xB0B4
319415
#define B_BE_RDU_CH6_INT BIT(28)
320416
#define B_BE_RDU_CH5_INT BIT(27)
@@ -1438,16 +1534,22 @@ u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
14381534
void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable);
14391535
void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
14401536
void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
1537+
void rtw89_pci_config_intr_mask_v2(struct rtw89_dev *rtwdev);
14411538
void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
14421539
void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
14431540
void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
14441541
void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1542+
void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1543+
void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
14451544
void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
14461545
struct rtw89_pci *rtwpci,
14471546
struct rtw89_pci_isrs *isrs);
14481547
void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
14491548
struct rtw89_pci *rtwpci,
14501549
struct rtw89_pci_isrs *isrs);
1550+
void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev,
1551+
struct rtw89_pci *rtwpci,
1552+
struct rtw89_pci_isrs *isrs);
14511553

14521554
static inline
14531555
u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev,

‎drivers/net/wireless/realtek/rtw89/reg.h

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3826,6 +3826,33 @@
38263826
#define B_BE_FS_GPIO17_INT_EN BIT(1)
38273827
#define B_BE_FS_GPIO16_INT_EN BIT(0)
38283828

3829+
#define R_BE_HIMR0 0x01A0
3830+
#define B_BE_WDT_DATACPU_TIMEOUT_INT_EN BIT(25)
3831+
#define B_BE_HALT_D2H_INT_EN BIT(24)
3832+
#define B_BE_WDT_TIMEOUT_INT_EN BIT(22)
3833+
#define B_BE_HALT_C2H_INT_EN BIT(21)
3834+
#define B_BE_RON_INT_EN BIT(20)
3835+
#define B_BE_PDNINT_EN BIT(19)
3836+
#define B_BE_SPSANA_OCP_INT_EN BIT(18)
3837+
#define B_BE_SPS_OCP_INT_EN BIT(17)
3838+
#define B_BE_BTON_STS_UPDATE_INT_EN BIT(16)
3839+
#define B_BE_GPIOF_INT_EN BIT(15)
3840+
#define B_BE_GPIOE_INT_EN BIT(14)
3841+
#define B_BE_GPIOD_INT_EN BIT(13)
3842+
#define B_BE_GPIOC_INT_EN BIT(12)
3843+
#define B_BE_GPIOB_INT_EN BIT(11)
3844+
#define B_BE_GPIOA_INT_EN BIT(10)
3845+
#define B_BE_GPIO9_INT_EN BIT(9)
3846+
#define B_BE_GPIO8_INT_EN BIT(8)
3847+
#define B_BE_GPIO7_INT_EN BIT(7)
3848+
#define B_BE_GPIO6_INT_EN BIT(6)
3849+
#define B_BE_GPIO5_INT_EN BIT(5)
3850+
#define B_BE_GPIO4_INT_EN BIT(4)
3851+
#define B_BE_GPIO3_INT_EN BIT(3)
3852+
#define B_BE_GPIO2_INT_EN BIT(2)
3853+
#define B_BE_GPIO1_INT_EN BIT(1)
3854+
#define B_BE_GPIO0_INT_EN BIT(0)
3855+
38293856
#define R_BE_HISR0 0x01A4
38303857
#define B_BE_WDT_DATACPU_TIMEOUT_INT BIT(25)
38313858
#define B_BE_HALT_D2H_INT BIT(24)

‎drivers/net/wireless/realtek/rtw89/rtw8922ae.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,10 @@ static const struct rtw89_pci_info rtw8922a_pci_info = {
5050

5151
.ltr_set = rtw89_pci_ltr_set_v2,
5252
.fill_txaddr_info = rtw89_pci_fill_txaddr_info_v1,
53+
.config_intr_mask = rtw89_pci_config_intr_mask_v2,
54+
.enable_intr = rtw89_pci_enable_intr_v2,
55+
.disable_intr = rtw89_pci_disable_intr_v2,
56+
.recognize_intrs = rtw89_pci_recognize_intrs_v2,
5357
};
5458

5559
static const struct rtw89_driver_info rtw89_8922ae_info = {

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