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bijudaslag-linaro
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mfd: rz-mtu3: Replace raw_spin_lock->spin_lock()
As per kernel documentation, use raw_spinlock_t only in real critical core code, low-level interrupt handling, and places where disabling preemption or interrupts is required. Here the lock is for concurrent register access from different drivers, hence spin_lock() is sufficient. Reported-by: Pavel Machek <[email protected]> Closes: https://lore.kernel.org/all/ZIL%[email protected]/ Signed-off-by: Biju Das <[email protected]> Reviewed-by: Pavel Machek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lee Jones <[email protected]>
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drivers/mfd/rz-mtu3.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
struct rz_mtu3_priv {
2323
void __iomem *mmio;
2424
struct reset_control *rstc;
25-
raw_spinlock_t lock;
25+
spinlock_t lock;
2626
};
2727

2828
/******* MTU3 registers (original offset is +0x1200) *******/
@@ -176,11 +176,11 @@ void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 offset,
176176
struct rz_mtu3_priv *priv = mtu->priv_data;
177177
unsigned long tmdr, flags;
178178

179-
raw_spin_lock_irqsave(&priv->lock, flags);
179+
spin_lock_irqsave(&priv->lock, flags);
180180
tmdr = rz_mtu3_shared_reg_read(ch, offset);
181181
__assign_bit(pos, &tmdr, !!val);
182182
rz_mtu3_shared_reg_write(ch, offset, tmdr);
183-
raw_spin_unlock_irqrestore(&priv->lock, flags);
183+
spin_unlock_irqrestore(&priv->lock, flags);
184184
}
185185
EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_update_bit);
186186

@@ -256,13 +256,13 @@ static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start)
256256
bitpos = rz_mtu3_get_tstr_bit_pos(ch);
257257

258258
/* start stop register shared by multiple timer channels */
259-
raw_spin_lock_irqsave(&priv->lock, flags);
259+
spin_lock_irqsave(&priv->lock, flags);
260260

261261
tstr = rz_mtu3_shared_reg_read(ch, offset);
262262
__assign_bit(bitpos, &tstr, start);
263263
rz_mtu3_shared_reg_write(ch, offset, tstr);
264264

265-
raw_spin_unlock_irqrestore(&priv->lock, flags);
265+
spin_unlock_irqrestore(&priv->lock, flags);
266266
}
267267

268268
bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
@@ -277,9 +277,9 @@ bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
277277
bitpos = rz_mtu3_get_tstr_bit_pos(ch);
278278

279279
/* start stop register shared by multiple timer channels */
280-
raw_spin_lock_irqsave(&priv->lock, flags);
280+
spin_lock_irqsave(&priv->lock, flags);
281281
tstr = rz_mtu3_shared_reg_read(ch, offset);
282-
raw_spin_unlock_irqrestore(&priv->lock, flags);
282+
spin_unlock_irqrestore(&priv->lock, flags);
283283

284284
return tstr & BIT(bitpos);
285285
}
@@ -349,7 +349,7 @@ static int rz_mtu3_probe(struct platform_device *pdev)
349349
return PTR_ERR(ddata->clk);
350350

351351
reset_control_deassert(priv->rstc);
352-
raw_spin_lock_init(&priv->lock);
352+
spin_lock_init(&priv->lock);
353353
platform_set_drvdata(pdev, ddata);
354354

355355
for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {

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