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Merge branch 'pci/controller/rcar'
- Add generic T_PVPERL macro for the required interval between power being stable and PERST# being inactive (Yoshihiro Shimoda) - Factor out dw_pcie_link_set_max_link_width() (Yoshihiro Shimoda) - Update PCI_EXP_LNKCAP_MLW so Link Capabilities shows the correct max link width (Yoshihiro Shimoda) - Drop tegra194 PCI_EXP_LNKCAP_MLW setting since dw_pcie_setup() already does it (Yoshihiro Shimoda) - Add dwc support for different dbi and dbi2 register offsets, to be used for R-Car Gen4 controllers (Yoshihiro Shimoda) - Add EDMA_UNROLL capability flag for R-Car Gen4 controllers that don't correctly advertise unrolled mapping via their eDMA CTRL register (Yoshihiro Shimoda) - Export dw_pcie_ep_exit() for use by the modular R-Car Gen4 driver (Yoshihiro Shimoda) - Add .pre_init() and .deinit() hooks for use by R-Car Gen4 controllers (Yoshihiro Shimoda) - Increase snps,dw-pcie DT reg and reg-names maxItems for R-Car Gen4 controllers (Yoshihiro Shimoda) - Add rcar-gen4-pci host and endpoint DT bindings and drivers (Yoshihiro Shimoda) - Add Renesas R8A779F0 Device ID to pci_endpoint_test to allow testing on R-Car S4-8 (Yoshihiro Shimoda) * pci/controller/rcar: misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 PCI: rcar-gen4: Add endpoint mode support PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host dt-bindings: PCI: dwc: Update maxItems of reg and reg-names PCI: dwc: endpoint: Introduce .pre_init() and .deinit() PCI: dwc: Expose dw_pcie_write_dbi2() to module PCI: dwc: Expose dw_pcie_ep_exit() to module PCI: dwc: Add EDMA_UNROLL capability flag PCI: dwc: endpoint: Add multiple PFs support for dbi2 PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling PCI: dwc: Add dw_pcie_link_set_max_link_width() PCI: Add T_PVPERL macro
2 parents eecffeb + 6c4b399 commit db20113

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‎Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022-2023 Renesas Electronics Corp.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas R-Car Gen4 PCIe Endpoint
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maintainers:
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- Yoshihiro Shimoda <[email protected]>
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allOf:
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- $ref: snps,dw-pcie-ep.yaml#
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properties:
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compatible:
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items:
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- const: renesas,r8a779f0-pcie-ep # R-Car S4-8
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- const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
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reg:
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maxItems: 7
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: dma
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- const: app
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- const: phy
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- const: addr_space
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interrupts:
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maxItems: 3
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interrupt-names:
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items:
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- const: dma
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- const: sft_ce
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- const: app
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: ref
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pwr
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max-link-speed:
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maximum: 4
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num-lanes:
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maximum: 4
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max-functions:
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maximum: 2
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- power-domains
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a779f0-sysc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie0_ep: pcie-ep@e65d0000 {
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compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
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reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
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<0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
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<0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
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<0 0xfe000000 0 0x400000>;
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reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
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interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma", "sft_ce", "app";
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clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
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clock-names = "core", "ref";
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power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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resets = <&cpg 624>;
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reset-names = "pwr";
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max-link-speed = <4>;
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num-lanes = <2>;
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max-functions = /bits/ 8 <2>;
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};
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};

‎Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022-2023 Renesas Electronics Corp.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas R-Car Gen4 PCIe Host
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maintainers:
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- Yoshihiro Shimoda <[email protected]>
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allOf:
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- $ref: snps,dw-pcie.yaml#
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properties:
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compatible:
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items:
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- const: renesas,r8a779f0-pcie # R-Car S4-8
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- const: renesas,rcar-gen4-pcie # R-Car Gen4
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reg:
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maxItems: 7
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: dma
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- const: app
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- const: phy
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- const: config
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interrupts:
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maxItems: 4
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interrupt-names:
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items:
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- const: msi
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- const: dma
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- const: sft_ce
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- const: app
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: ref
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pwr
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max-link-speed:
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maximum: 4
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num-lanes:
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maximum: 4
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- power-domains
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a779f0-sysc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie: pcie@e65d0000 {
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compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
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reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
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<0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
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<0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
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<0 0xfe000000 0 0x400000>;
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reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
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interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi", "dma", "sft_ce", "app";
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clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
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clock-names = "core", "ref";
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power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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resets = <&cpg 624>;
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reset-names = "pwr";
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max-link-speed = <4>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
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<0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
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dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
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snps,enable-cdm-check;
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};
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};

‎Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

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specific for each activated function, while the rest of the sub-spaces
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are common for all of them (if there are more than one).
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minItems: 2
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maxItems: 6
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maxItems: 7
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reg-names:
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minItems: 2
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maxItems: 6
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maxItems: 7
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interrupts:
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description:

‎Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

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normal controller functioning. iATU memory IO region is also required
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if the space is unrolled (IP-core version >= 4.80a).
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minItems: 2
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maxItems: 5
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maxItems: 7
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reg-names:
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minItems: 2
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maxItems: 5
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maxItems: 7
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items:
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oneOf:
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- description:

‎Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

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are required for the normal controller work. iATU memory IO region is
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also required if the space is unrolled (IP-core version >= 4.80a).
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minItems: 2
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maxItems: 5
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maxItems: 7
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reg-names:
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minItems: 2
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maxItems: 5
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maxItems: 7
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items:
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oneOf:
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- description:

‎MAINTAINERS

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S: Maintained
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F: Documentation/devicetree/bindings/pci/*rcar*
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F: drivers/pci/controller/*rcar*
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F: drivers/pci/controller/dwc/*rcar*
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PCI DRIVER FOR SAMSUNG EXYNOS
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M: Jingoo Han <[email protected]>

‎drivers/misc/pci_endpoint_test.c

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#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
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#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
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#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
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#define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
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static DEFINE_IDA(pci_endpoint_test_ida);
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{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
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{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
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{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
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{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
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.driver_data = (kernel_ulong_t)&default_data,
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},
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
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.driver_data = (kernel_ulong_t)&j721e_data,
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},

‎drivers/pci/controller/dwc/Kconfig

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to work in endpoint mode. The PCIe controller uses the DesignWare core
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plus Qualcomm-specific hardware wrappers.
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config PCIE_RCAR_GEN4
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tristate
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config PCIE_RCAR_GEN4_HOST
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tristate "Renesas R-Car Gen4 PCIe controller (host mode)"
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depends on ARCH_RENESAS || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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select PCIE_RCAR_GEN4
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help
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Say Y here if you want PCIe controller (host mode) on R-Car Gen4 SoCs.
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To compile this driver as a module, choose M here: the module will be
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called pcie-rcar-gen4.ko. This uses the DesignWare core.
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config PCIE_RCAR_GEN4_EP
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tristate "Renesas R-Car Gen4 PCIe controller (endpoint mode)"
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depends on ARCH_RENESAS || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_RCAR_GEN4
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help
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Say Y here if you want PCIe controller (endpoint mode) on R-Car Gen4
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SoCs. To compile this driver as a module, choose M here: the module
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will be called pcie-rcar-gen4.ko. This uses the DesignWare core.
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config PCIE_ROCKCHIP_DW_HOST
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bool "Rockchip DesignWare PCIe controller"
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select PCIE_DW

‎drivers/pci/controller/dwc/Makefile

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@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
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obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
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obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
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obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
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obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.

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