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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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+ #include <linux/property.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#define PIN_CFG_IO_VMC_QSPI BIT(7)
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#define PIN_CFG_IO_VMC_ETH0 BIT(8)
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#define PIN_CFG_IO_VMC_ETH1 BIT(9)
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- #define PIN_CFG_FILONOFF BIT(10)
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- #define PIN_CFG_FILNUM BIT(11)
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- #define PIN_CFG_FILCLKSEL BIT(12)
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- #define PIN_CFG_IOLH_C BIT(13)
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- #define PIN_CFG_SOFT_PS BIT(14)
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- #define PIN_CFG_OEN BIT(15)
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- #define PIN_CFG_NOGPIO_INT BIT(16)
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- #define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */
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- #define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */
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- #define PIN_CFG_ELC BIT(19)
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- #define PIN_CFG_IOLH_RZV2H BIT(20)
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+ #define PIN_CFG_NF BIT(10) /* Digital noise filter */
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+ #define PIN_CFG_IOLH_C BIT(11)
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+ #define PIN_CFG_SOFT_PS BIT(12)
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+ #define PIN_CFG_OEN BIT(13)
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+ #define PIN_CFG_NOGPIO_INT BIT(14)
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+ #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
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+ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
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+ #define PIN_CFG_ELC BIT(17)
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+ #define PIN_CFG_IOLH_RZV2H BIT(18)
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#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
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#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
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#define RZG2L_MPXED_COMMON_PIN_FUNCS (group ) \
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(PIN_CFG_IOLH_##group | \
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PIN_CFG_PUPD | \
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- PIN_CFG_FILONOFF | \
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- PIN_CFG_FILNUM | \
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- PIN_CFG_FILCLKSEL)
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+ PIN_CFG_NF)
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#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
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PIN_CFG_SR)
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PIN_CFG_SR | \
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PIN_CFG_SMT)
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- #define RZG2L_MPXED_ETH_PIN_FUNCS (x ) ((x) | \
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- PIN_CFG_FILONOFF | \
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- PIN_CFG_FILNUM | \
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- PIN_CFG_FILCLKSEL)
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+ #define RZG2L_MPXED_ETH_PIN_FUNCS (x ) ((x) | PIN_CFG_NF)
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#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
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#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
@@ -394,13 +388,13 @@ static const u64 r9a09g057_variable_pin_cfg[] = {
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#ifdef CONFIG_RISCV
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static const u64 r9a07g043f_variable_pin_cfg [] = {
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RZG2L_VARIABLE_PIN_CFG_PACK (20 , 0 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
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+ PIN_CFG_NF |
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PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ),
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RZG2L_VARIABLE_PIN_CFG_PACK (20 , 1 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
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+ PIN_CFG_NF |
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PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ),
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RZG2L_VARIABLE_PIN_CFG_PACK (20 , 2 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
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+ PIN_CFG_NF |
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PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ),
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RZG2L_VARIABLE_PIN_CFG_PACK (20 , 3 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ),
@@ -431,7 +425,7 @@ static const u64 r9a07g043f_variable_pin_cfg[] = {
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RZG2L_VARIABLE_PIN_CFG_PACK (24 , 4 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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PIN_CFG_NOGPIO_INT ),
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RZG2L_VARIABLE_PIN_CFG_PACK (24 , 5 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
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+ PIN_CFG_NF |
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PIN_CFG_NOGPIO_INT ),
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};
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#endif
@@ -528,8 +522,7 @@ static int rzg2l_map_add_config(struct pinctrl_map *map,
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{
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unsigned long * cfgs ;
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- cfgs = kmemdup (configs , num_configs * sizeof (* cfgs ),
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- GFP_KERNEL );
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+ cfgs = kmemdup_array (configs , num_configs , sizeof (* cfgs ), GFP_KERNEL );
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if (!cfgs )
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return - ENOMEM ;
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@@ -1392,9 +1385,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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for (i = 0 ; i < num_configs ; i ++ ) {
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param = pinconf_to_config_param (_configs [i ]);
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+ arg = pinconf_to_config_argument (_configs [i ]);
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switch (param ) {
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case PIN_CONFIG_INPUT_ENABLE :
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- arg = pinconf_to_config_argument (_configs [i ]);
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if (!(cfg & PIN_CFG_IEN ))
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return - EINVAL ;
@@ -1403,7 +1396,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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break ;
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case PIN_CONFIG_OUTPUT_ENABLE :
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- arg = pinconf_to_config_argument (_configs [i ]);
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if (!(cfg & PIN_CFG_OEN ))
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return - EINVAL ;
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if (!pctrl -> data -> oen_write )
@@ -1414,12 +1406,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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break ;
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case PIN_CONFIG_POWER_SOURCE :
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- settings .power_source = pinconf_to_config_argument ( _configs [ i ]) ;
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+ settings .power_source = arg ;
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break ;
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case PIN_CONFIG_SLEW_RATE :
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- arg = pinconf_to_config_argument (_configs [i ]);
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-
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if (!(cfg & PIN_CFG_SR ) || arg > 1 )
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return - EINVAL ;
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@@ -1440,8 +1430,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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break ;
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case PIN_CONFIG_DRIVE_STRENGTH :
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- arg = pinconf_to_config_argument (_configs [i ]);
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-
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if (!(cfg & PIN_CFG_IOLH_A ) || hwcfg -> drive_strength_ua )
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return - EINVAL ;
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@@ -1461,12 +1449,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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!hwcfg -> drive_strength_ua )
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return - EINVAL ;
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- settings .drive_strength_ua = pinconf_to_config_argument ( _configs [ i ]) ;
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+ settings .drive_strength_ua = arg ;
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break ;
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case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS :
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- arg = pinconf_to_config_argument (_configs [i ]);
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-
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if (!(cfg & PIN_CFG_IOLH_B ) || !hwcfg -> iolh_groupb_oi [0 ])
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return - EINVAL ;
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@@ -1484,7 +1470,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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if (!(cfg & PIN_CFG_IOLH_RZV2H ))
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return - EINVAL ;
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- arg = pinconf_to_config_argument (_configs [i ]);
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if (arg > 3 )
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return - EINVAL ;
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rzg2l_rmw_pin_config (pctrl , IOLH (off ), bit , IOLH_MASK , arg );
@@ -1887,17 +1872,15 @@ static const u64 r9a07g043_gpio_configs[] = {
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#ifdef CONFIG_RISCV
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/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
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RZG2L_GPIO_PORT_SPARSE_PACK (0x2 , 0x06 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
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- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ), /* P19 */
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+ PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ), /* P19 */
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RZG2L_GPIO_PORT_PACK_VARIABLE (8 , 0x07 ), /* P20 */
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RZG2L_GPIO_PORT_SPARSE_PACK (0x2 , 0x08 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ), /* P21 */
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RZG2L_GPIO_PORT_PACK (4 , 0x09 , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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PIN_CFG_IEN | PIN_CFG_NOGPIO_INT ), /* P22 */
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RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE (0x3e , 0x0a ), /* P23 */
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RZG2L_GPIO_PORT_PACK_VARIABLE (6 , 0x0b ), /* P24 */
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- RZG2L_GPIO_PORT_SPARSE_PACK (0x2 , 0x0c , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
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- PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
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+ RZG2L_GPIO_PORT_SPARSE_PACK (0x2 , 0x0c , PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |
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PIN_CFG_NOGPIO_INT ), /* P25 */
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0x0 , /* P26 */
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0x0 , /* P27 */
@@ -1975,8 +1958,7 @@ static const struct {
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struct rzg2l_dedicated_configs rzg2l_pins [7 ];
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} rzg2l_dedicated_pins = {
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.common = {
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- { "NMI" , RZG2L_SINGLE_PIN_PACK (0x1 , 0 ,
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- (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL )) },
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+ { "NMI" , RZG2L_SINGLE_PIN_PACK (0x1 , 0 , PIN_CFG_NF ) },
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{ "TMS/SWDIO" , RZG2L_SINGLE_PIN_PACK (0x2 , 0 ,
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(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN )) },
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{ "TDO" , RZG2L_SINGLE_PIN_PACK (0x3 , 0 ,
@@ -2057,8 +2039,7 @@ static const struct {
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};
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static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins [] = {
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- { "NMI" , RZG2L_SINGLE_PIN_PACK (0x0 , 0 , (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
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- PIN_CFG_FILCLKSEL )) },
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+ { "NMI" , RZG2L_SINGLE_PIN_PACK (0x0 , 0 , PIN_CFG_NF ) },
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{ "TMS/SWDIO" , RZG2L_SINGLE_PIN_PACK (0x1 , 0 , (PIN_CFG_IOLH_A | PIN_CFG_IEN |
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PIN_CFG_SOFT_PS )) },
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{ "TDO" , RZG2L_SINGLE_PIN_PACK (0x1 , 1 , (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS )) },
@@ -2097,8 +2078,7 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
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};
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static struct rzg2l_dedicated_configs rzv2h_dedicated_pins [] = {
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- { "NMI" , RZG2L_SINGLE_PIN_PACK (0x1 , 0 , (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
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- PIN_CFG_FILCLKSEL )) },
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+ { "NMI" , RZG2L_SINGLE_PIN_PACK (0x1 , 0 , PIN_CFG_NF ) },
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{ "TMS_SWDIO" , RZG2L_SINGLE_PIN_PACK (0x3 , 0 , (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_IEN )) },
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{ "TDO" , RZG2L_SINGLE_PIN_PACK (0x3 , 2 , (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR )) },
@@ -2624,7 +2604,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
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girq = & chip -> irq ;
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gpio_irq_chip_set_chip (girq , & rzg2l_gpio_irqchip );
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- girq -> fwnode = of_node_to_fwnode ( np );
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+ girq -> fwnode = dev_fwnode ( pctrl -> dev );
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girq -> parent_domain = parent_domain ;
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girq -> child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq ;
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girq -> populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec ;
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