Skip to content

Commit e87eb58

Browse files
bjorn-helgaasbjorn-helgaas
committed
Merge branch 'pci/misc'
 - Add NumaChip SPDX header (Krzysztof Wilczynski) - Replace EXTRA_CFLAGS with ccflags-y (Krzysztof Wilczynski) - Remove unused includes (Krzysztof Wilczynski) - Avoid AMD FCH XHCI USB PME# from D0 defect that prevents wakeup on USB 2.0 or 1.1 connect events (Kai-Heng Feng) - Removed unused sysfs attribute groups (Ben Dooks) - Remove PTM and ASPM dependencies on PCIEPORTBUS (Bjorn Helgaas) - Add PCIe Link Control 2 register field definitions to replace magic numbers in AMDGPU and Radeon CIK/SI (Bjorn Helgaas) - Fix incorrect Link Control 2 Transmit Margin usage in AMDGPU and Radeon CIK/SI PCIe Gen3 link training (Bjorn Helgaas) - Use pcie_capability_read_word() instead of pci_read_config_word() in AMDGPU and Radeon CIK/SI (Frederick Lawler) * pci/misc: drm/radeon: Prefer pcie_capability_read_word() drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions drm/radeon: Correct Transmit Margin masks drm/amdgpu: Prefer pcie_capability_read_word() drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions drm/amdgpu: Correct Transmit Margin masks PCI: Add #defines for Enter Compliance, Transmit Margin PCI: Allow building PCIe things without PCIEPORTBUS PCI: Remove PCIe Kconfig dependencies on PCI PCI/ASPM: Remove dependency on PCIEPORTBUS PCI/PTM: Remove dependency on PCIEPORTBUS PCI/PTM: Remove spurious "d" from granularity message PCI: sysfs: Remove unused attribute groups x86/PCI: Avoid AMD FCH XHCI USB PME# from D0 defect PCI: Remove unused includes and superfluous struct declaration x86/PCI: Replace deprecated EXTRA_CFLAGS with ccflags-y x86/PCI: Correct SPDX comment style x86/PCI: Add NumaChip SPDX GPL-2.0 to replace COPYING boilerplate
2 parents 2df0882 + 3d581b1 commit e87eb58

File tree

23 files changed

+272
-177
lines changed

23 files changed

+272
-177
lines changed

‎arch/x86/pci/Makefile

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,4 @@ obj-y += bus_numa.o
2424
obj-$(CONFIG_AMD_NB) += amd_bus.o
2525
obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o
2626

27-
ifeq ($(CONFIG_PCI_DEBUG),y)
28-
EXTRA_CFLAGS += -DDEBUG
29-
endif
27+
ccflags-$(CONFIG_PCI_DEBUG) += -DDEBUG

‎arch/x86/pci/fixup.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -588,6 +588,17 @@ static void pci_fixup_amd_ehci_pme(struct pci_dev *dev)
588588
}
589589
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);
590590

591+
/*
592+
* Device [1022:7914]
593+
* When in D0, PME# doesn't get asserted when plugging USB 2.0 device.
594+
*/
595+
static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev)
596+
{
597+
dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");
598+
dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
599+
}
600+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);
601+
591602
/*
592603
* Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
593604
*

‎arch/x86/pci/numachip.c

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1+
// SPDX-License-Identifier: GPL-2.0
12
/*
2-
* This file is subject to the terms and conditions of the GNU General Public
3-
* License. See the file "COPYING" in the main directory of this archive
4-
* for more details.
5-
*
63
* Numascale NumaConnect-specific PCI code
74
*
85
* Copyright (C) 2012 Numascale AS. All rights reserved.

‎drivers/gpu/drm/amd/amdgpu/cik.c

Lines changed: 60 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1384,7 +1384,6 @@ static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
13841384
static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
13851385
{
13861386
struct pci_dev *root = adev->pdev->bus->self;
1387-
int bridge_pos, gpu_pos;
13881387
u32 speed_cntl, current_data_rate;
13891388
int i;
13901389
u16 tmp16;
@@ -1419,12 +1418,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
14191418
DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
14201419
}
14211420

1422-
bridge_pos = pci_pcie_cap(root);
1423-
if (!bridge_pos)
1424-
return;
1425-
1426-
gpu_pos = pci_pcie_cap(adev->pdev);
1427-
if (!gpu_pos)
1421+
if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
14281422
return;
14291423

14301424
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
@@ -1434,14 +1428,17 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
14341428
u16 bridge_cfg2, gpu_cfg2;
14351429
u32 max_lw, current_lw, tmp;
14361430

1437-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1438-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1431+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
1432+
&bridge_cfg);
1433+
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
1434+
&gpu_cfg);
14391435

14401436
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1441-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1437+
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
14421438

14431439
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1444-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1440+
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
1441+
tmp16);
14451442

14461443
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
14471444
max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
@@ -1465,15 +1462,23 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
14651462

14661463
for (i = 0; i < 10; i++) {
14671464
/* check status */
1468-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1465+
pcie_capability_read_word(adev->pdev,
1466+
PCI_EXP_DEVSTA,
1467+
&tmp16);
14691468
if (tmp16 & PCI_EXP_DEVSTA_TRPND)
14701469
break;
14711470

1472-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1473-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1471+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
1472+
&bridge_cfg);
1473+
pcie_capability_read_word(adev->pdev,
1474+
PCI_EXP_LNKCTL,
1475+
&gpu_cfg);
14741476

1475-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1476-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1477+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
1478+
&bridge_cfg2);
1479+
pcie_capability_read_word(adev->pdev,
1480+
PCI_EXP_LNKCTL2,
1481+
&gpu_cfg2);
14771482

14781483
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
14791484
tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@@ -1486,26 +1491,45 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
14861491
msleep(100);
14871492

14881493
/* linkctl */
1489-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1494+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
1495+
&tmp16);
14901496
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
14911497
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1492-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1498+
pcie_capability_write_word(root, PCI_EXP_LNKCTL,
1499+
tmp16);
14931500

1494-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1501+
pcie_capability_read_word(adev->pdev,
1502+
PCI_EXP_LNKCTL,
1503+
&tmp16);
14951504
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
14961505
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1497-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1506+
pcie_capability_write_word(adev->pdev,
1507+
PCI_EXP_LNKCTL,
1508+
tmp16);
14981509

14991510
/* linkctl2 */
1500-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1501-
tmp16 &= ~((1 << 4) | (7 << 9));
1502-
tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1503-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1504-
1505-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1506-
tmp16 &= ~((1 << 4) | (7 << 9));
1507-
tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1508-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1511+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
1512+
&tmp16);
1513+
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
1514+
PCI_EXP_LNKCTL2_TX_MARGIN);
1515+
tmp16 |= (bridge_cfg2 &
1516+
(PCI_EXP_LNKCTL2_ENTER_COMP |
1517+
PCI_EXP_LNKCTL2_TX_MARGIN));
1518+
pcie_capability_write_word(root,
1519+
PCI_EXP_LNKCTL2,
1520+
tmp16);
1521+
1522+
pcie_capability_read_word(adev->pdev,
1523+
PCI_EXP_LNKCTL2,
1524+
&tmp16);
1525+
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
1526+
PCI_EXP_LNKCTL2_TX_MARGIN);
1527+
tmp16 |= (gpu_cfg2 &
1528+
(PCI_EXP_LNKCTL2_ENTER_COMP |
1529+
PCI_EXP_LNKCTL2_TX_MARGIN));
1530+
pcie_capability_write_word(adev->pdev,
1531+
PCI_EXP_LNKCTL2,
1532+
tmp16);
15091533

15101534
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
15111535
tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@@ -1520,15 +1544,16 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
15201544
speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
15211545
WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
15221546

1523-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1524-
tmp16 &= ~0xf;
1547+
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
1548+
tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
1549+
15251550
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1526-
tmp16 |= 3; /* gen3 */
1551+
tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
15271552
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1528-
tmp16 |= 2; /* gen2 */
1553+
tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
15291554
else
1530-
tmp16 |= 1; /* gen1 */
1531-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1555+
tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
1556+
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
15321557

15331558
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
15341559
speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;

‎drivers/gpu/drm/amd/amdgpu/si.c

Lines changed: 61 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1633,7 +1633,6 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
16331633
static void si_pcie_gen3_enable(struct amdgpu_device *adev)
16341634
{
16351635
struct pci_dev *root = adev->pdev->bus->self;
1636-
int bridge_pos, gpu_pos;
16371636
u32 speed_cntl, current_data_rate;
16381637
int i;
16391638
u16 tmp16;
@@ -1668,12 +1667,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
16681667
DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
16691668
}
16701669

1671-
bridge_pos = pci_pcie_cap(root);
1672-
if (!bridge_pos)
1673-
return;
1674-
1675-
gpu_pos = pci_pcie_cap(adev->pdev);
1676-
if (!gpu_pos)
1670+
if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
16771671
return;
16781672

16791673
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
@@ -1682,14 +1676,17 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
16821676
u16 bridge_cfg2, gpu_cfg2;
16831677
u32 max_lw, current_lw, tmp;
16841678

1685-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1686-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1679+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
1680+
&bridge_cfg);
1681+
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
1682+
&gpu_cfg);
16871683

16881684
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1689-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1685+
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
16901686

16911687
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1692-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1688+
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
1689+
tmp16);
16931690

16941691
tmp = RREG32_PCIE(PCIE_LC_STATUS1);
16951692
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -1706,15 +1703,23 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
17061703
}
17071704

17081705
for (i = 0; i < 10; i++) {
1709-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1706+
pcie_capability_read_word(adev->pdev,
1707+
PCI_EXP_DEVSTA,
1708+
&tmp16);
17101709
if (tmp16 & PCI_EXP_DEVSTA_TRPND)
17111710
break;
17121711

1713-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1714-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1712+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
1713+
&bridge_cfg);
1714+
pcie_capability_read_word(adev->pdev,
1715+
PCI_EXP_LNKCTL,
1716+
&gpu_cfg);
17151717

1716-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1717-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1718+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
1719+
&bridge_cfg2);
1720+
pcie_capability_read_word(adev->pdev,
1721+
PCI_EXP_LNKCTL2,
1722+
&gpu_cfg2);
17181723

17191724
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
17201725
tmp |= LC_SET_QUIESCE;
@@ -1726,25 +1731,44 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
17261731

17271732
mdelay(100);
17281733

1729-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1734+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
1735+
&tmp16);
17301736
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
17311737
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1732-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1738+
pcie_capability_write_word(root, PCI_EXP_LNKCTL,
1739+
tmp16);
17331740

1734-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1741+
pcie_capability_read_word(adev->pdev,
1742+
PCI_EXP_LNKCTL,
1743+
&tmp16);
17351744
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
17361745
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1737-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1738-
1739-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1740-
tmp16 &= ~((1 << 4) | (7 << 9));
1741-
tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1742-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1743-
1744-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1745-
tmp16 &= ~((1 << 4) | (7 << 9));
1746-
tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1747-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1746+
pcie_capability_write_word(adev->pdev,
1747+
PCI_EXP_LNKCTL,
1748+
tmp16);
1749+
1750+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
1751+
&tmp16);
1752+
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
1753+
PCI_EXP_LNKCTL2_TX_MARGIN);
1754+
tmp16 |= (bridge_cfg2 &
1755+
(PCI_EXP_LNKCTL2_ENTER_COMP |
1756+
PCI_EXP_LNKCTL2_TX_MARGIN));
1757+
pcie_capability_write_word(root,
1758+
PCI_EXP_LNKCTL2,
1759+
tmp16);
1760+
1761+
pcie_capability_read_word(adev->pdev,
1762+
PCI_EXP_LNKCTL2,
1763+
&tmp16);
1764+
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
1765+
PCI_EXP_LNKCTL2_TX_MARGIN);
1766+
tmp16 |= (gpu_cfg2 &
1767+
(PCI_EXP_LNKCTL2_ENTER_COMP |
1768+
PCI_EXP_LNKCTL2_TX_MARGIN));
1769+
pcie_capability_write_word(adev->pdev,
1770+
PCI_EXP_LNKCTL2,
1771+
tmp16);
17481772

17491773
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
17501774
tmp &= ~LC_SET_QUIESCE;
@@ -1757,15 +1781,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
17571781
speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
17581782
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
17591783

1760-
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1761-
tmp16 &= ~0xf;
1784+
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
1785+
tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
1786+
17621787
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1763-
tmp16 |= 3;
1788+
tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
17641789
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1765-
tmp16 |= 2;
1790+
tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
17661791
else
1767-
tmp16 |= 1;
1768-
pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1792+
tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
1793+
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
17691794

17701795
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
17711796
speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

0 commit comments

Comments
 (0)