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johnharr-inteljohnharr-intel
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drm/i915/gt: More use of GT specific print helpers
A bunch of print messages got missed in the update to using sub-system specific helpers. So update those. Signed-off-by: John Harrison <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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-43
lines changed

5 files changed

+39
-43
lines changed

‎drivers/gpu/drm/i915/gt/intel_engine_cs.c

Lines changed: 12 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -316,10 +316,9 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
316316
* out in the wash.
317317
*/
318318
cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
319-
drm_dbg(&gt->i915->drm,
320-
"graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
321-
GRAPHICS_VER(gt->i915), cxt_size * 64,
322-
cxt_size - 1);
319+
gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
320+
GRAPHICS_VER(gt->i915), cxt_size * 64,
321+
cxt_size - 1);
323322
return round_up(cxt_size * 64, PAGE_SIZE);
324323
case 3:
325324
case 2:
@@ -788,16 +787,15 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
788787

789788
if (!(BIT(i) & vdbox_mask)) {
790789
gt->info.engine_mask &= ~BIT(_VCS(i));
791-
drm_dbg(&i915->drm, "vcs%u fused off\n", i);
790+
gt_dbg(gt, "vcs%u fused off\n", i);
792791
continue;
793792
}
794793

795794
if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
796795
gt->info.vdbox_sfc_access |= BIT(i);
797796
logical_vdbox++;
798797
}
799-
drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
800-
vdbox_mask, VDBOX_MASK(gt));
798+
gt_dbg(gt, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt));
801799
GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
802800

803801
for (i = 0; i < I915_MAX_VECS; i++) {
@@ -808,11 +806,10 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
808806

809807
if (!(BIT(i) & vebox_mask)) {
810808
gt->info.engine_mask &= ~BIT(_VECS(i));
811-
drm_dbg(&i915->drm, "vecs%u fused off\n", i);
809+
gt_dbg(gt, "vecs%u fused off\n", i);
812810
}
813811
}
814-
drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
815-
vebox_mask, VEBOX_MASK(gt));
812+
gt_dbg(gt, "vebox enable: %04x, instances: %04lx\n", vebox_mask, VEBOX_MASK(gt));
816813
GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
817814
}
818815

@@ -838,7 +835,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
838835
*/
839836
for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
840837
info->engine_mask &= ~BIT(_CCS(i));
841-
drm_dbg(&i915->drm, "ccs%u fused off\n", i);
838+
gt_dbg(gt, "ccs%u fused off\n", i);
842839
}
843840
}
844841

@@ -866,8 +863,8 @@ static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
866863
_BCS(instance));
867864

868865
if (mask & info->engine_mask) {
869-
drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
870-
drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
866+
gt_dbg(gt, "bcs%u fused off\n", instance);
867+
gt_dbg(gt, "bcs%u fused off\n", instance + 1);
871868

872869
info->engine_mask &= ~mask;
873870
}
@@ -907,8 +904,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
907904
* submission, which will wake up the GSC power well.
908905
*/
909906
if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(&gt->uc)) {
910-
drm_notice(&gt->i915->drm,
911-
"No GSC FW selected, disabling GSC CS and media C6\n");
907+
gt_notice(gt, "No GSC FW selected, disabling GSC CS and media C6\n");
912908
info->engine_mask &= ~BIT(GSC0);
913909
}
914910

@@ -1097,8 +1093,7 @@ static int init_status_page(struct intel_engine_cs *engine)
10971093
*/
10981094
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
10991095
if (IS_ERR(obj)) {
1100-
drm_err(&engine->i915->drm,
1101-
"Failed to allocate status page\n");
1096+
gt_err(engine->gt, "Failed to allocate status page\n");
11021097
return PTR_ERR(obj);
11031098
}
11041099

‎drivers/gpu/drm/i915/gt/intel_gsc.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include "gem/i915_gem_region.h"
1212
#include "gt/intel_gsc.h"
1313
#include "gt/intel_gt.h"
14+
#include "gt/intel_gt_print.h"
1415

1516
#define GSC_BAR_LENGTH 0x00000FFC
1617

@@ -49,13 +50,13 @@ gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size
4950
I915_BO_ALLOC_CONTIGUOUS |
5051
I915_BO_ALLOC_CPU_CLEAR);
5152
if (IS_ERR(obj)) {
52-
drm_err(&gt->i915->drm, "Failed to allocate gsc memory\n");
53+
gt_err(gt, "Failed to allocate gsc memory\n");
5354
return PTR_ERR(obj);
5455
}
5556

5657
err = i915_gem_object_pin_pages_unlocked(obj);
5758
if (err) {
58-
drm_err(&gt->i915->drm, "Failed to pin pages for gsc memory\n");
59+
gt_err(gt, "Failed to pin pages for gsc memory\n");
5960
goto out_put;
6061
}
6162

@@ -286,12 +287,12 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
286287
int ret;
287288

288289
if (intf_id >= INTEL_GSC_NUM_INTERFACES) {
289-
drm_warn_once(&gt->i915->drm, "GSC irq: intf_id %d is out of range", intf_id);
290+
gt_warn_once(gt, "GSC irq: intf_id %d is out of range", intf_id);
290291
return;
291292
}
292293

293294
if (!HAS_HECI_GSC(gt->i915)) {
294-
drm_warn_once(&gt->i915->drm, "GSC irq: not supported");
295+
gt_warn_once(gt, "GSC irq: not supported");
295296
return;
296297
}
297298

@@ -300,7 +301,7 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
300301

301302
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
302303
if (ret)
303-
drm_err_ratelimited(&gt->i915->drm, "error handling GSC irq: %d\n", ret);
304+
gt_err_ratelimited(gt, "error handling GSC irq: %d\n", ret);
304305
}
305306

306307
void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir)

‎drivers/gpu/drm/i915/gt/intel_gt_print.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,9 @@
1616
#define gt_warn(_gt, _fmt, ...) \
1717
drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
1818

19+
#define gt_warn_once(_gt, _fmt, ...) \
20+
drm_warn_once(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
21+
1922
#define gt_notice(_gt, _fmt, ...) \
2023
drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
2124

‎drivers/gpu/drm/i915/gt/intel_reset.c

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#include "intel_engine_regs.h"
2727
#include "intel_gt.h"
2828
#include "intel_gt_pm.h"
29+
#include "intel_gt_print.h"
2930
#include "intel_gt_requests.h"
3031
#include "intel_mchbar_regs.h"
3132
#include "intel_pci_config.h"
@@ -592,10 +593,10 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
592593
ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
593594
700, 0, NULL);
594595
if (ret)
595-
drm_err(&engine->i915->drm,
596-
"%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
597-
engine->name, request,
598-
intel_uncore_read_fw(uncore, reg));
596+
gt_err(engine->gt,
597+
"%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
598+
engine->name, request,
599+
intel_uncore_read_fw(uncore, reg));
599600

600601
return ret;
601602
}
@@ -1199,25 +1200,24 @@ void intel_gt_reset(struct intel_gt *gt,
11991200
goto unlock;
12001201

12011202
if (reason)
1202-
drm_notice(&gt->i915->drm,
1203-
"Resetting chip for %s\n", reason);
1203+
gt_notice(gt, "Resetting chip for %s\n", reason);
12041204
atomic_inc(&gt->i915->gpu_error.reset_count);
12051205

12061206
awake = reset_prepare(gt);
12071207

12081208
if (!intel_has_gpu_reset(gt)) {
12091209
if (gt->i915->params.reset)
1210-
drm_err(&gt->i915->drm, "GPU reset not supported\n");
1210+
gt_err(gt, "GPU reset not supported\n");
12111211
else
1212-
drm_dbg(&gt->i915->drm, "GPU reset disabled\n");
1212+
gt_dbg(gt, "GPU reset disabled\n");
12131213
goto error;
12141214
}
12151215

12161216
if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
12171217
intel_runtime_pm_disable_interrupts(gt->i915);
12181218

12191219
if (do_reset(gt, stalled_mask)) {
1220-
drm_err(&gt->i915->drm, "Failed to reset chip\n");
1220+
gt_err(gt, "Failed to reset chip\n");
12211221
goto taint;
12221222
}
12231223

@@ -1236,9 +1236,7 @@ void intel_gt_reset(struct intel_gt *gt,
12361236
*/
12371237
ret = intel_gt_init_hw(gt);
12381238
if (ret) {
1239-
drm_err(&gt->i915->drm,
1240-
"Failed to initialise HW following reset (%d)\n",
1241-
ret);
1239+
gt_err(gt, "Failed to initialise HW following reset (%d)\n", ret);
12421240
goto taint;
12431241
}
12441242

@@ -1605,9 +1603,7 @@ static void intel_wedge_me(struct work_struct *work)
16051603
{
16061604
struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
16071605

1608-
drm_err(&w->gt->i915->drm,
1609-
"%s timed out, cancelling all in-flight rendering.\n",
1610-
w->name);
1606+
gt_err(w->gt, "%s timed out, cancelling all in-flight rendering.\n", w->name);
16111607
intel_gt_set_wedged(w->gt);
16121608
}
16131609

‎drivers/gpu/drm/i915/gt/intel_workarounds.c

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include "intel_gpu_commands.h"
1212
#include "intel_gt.h"
1313
#include "intel_gt_mcr.h"
14+
#include "intel_gt_print.h"
1415
#include "intel_gt_regs.h"
1516
#include "intel_ring.h"
1617
#include "intel_workarounds.h"
@@ -119,8 +120,8 @@ static void wa_init_finish(struct i915_wa_list *wal)
119120
if (!wal->count)
120121
return;
121122

122-
drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n",
123-
wal->wa_count, wal->name, wal->engine_name);
123+
gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n",
124+
wal->wa_count, wal->name, wal->engine_name);
124125
}
125126

126127
static enum forcewake_domains
@@ -1779,10 +1780,10 @@ wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur,
17791780
const char *name, const char *from)
17801781
{
17811782
if ((cur ^ wa->set) & wa->read) {
1782-
drm_err(&gt->i915->drm,
1783-
"%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n",
1784-
name, from, i915_mmio_reg_offset(wa->reg),
1785-
cur, cur & wa->read, wa->set & wa->read);
1783+
gt_err(gt,
1784+
"%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n",
1785+
name, from, i915_mmio_reg_offset(wa->reg),
1786+
cur, cur & wa->read, wa->set & wa->read);
17861787

17871788
return false;
17881789
}

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