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33 | 33 |
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34 | 34 | #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
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35 | 35 |
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36 |
| -/** |
37 |
| - * enum icst_control_type - the type of ICST control register |
38 |
| - */ |
39 |
| -enum icst_control_type { |
40 |
| - ICST_VERSATILE, /* The standard type, all control bits available */ |
41 |
| - ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */ |
42 |
| - ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */ |
43 |
| - ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */ |
44 |
| - ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */ |
45 |
| - ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */ |
46 |
| -}; |
47 |
| - |
48 | 36 | /**
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49 | 37 | * struct clk_icst - ICST VCO clock wrapper
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50 | 38 | * @hw: corresponding clock hardware entry
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@@ -344,12 +332,12 @@ static const struct clk_ops icst_ops = {
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344 | 332 | .set_rate = icst_set_rate,
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345 | 333 | };
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346 | 334 |
|
347 |
| -static struct clk *icst_clk_setup(struct device *dev, |
348 |
| - const struct clk_icst_desc *desc, |
349 |
| - const char *name, |
350 |
| - const char *parent_name, |
351 |
| - struct regmap *map, |
352 |
| - enum icst_control_type ctype) |
| 335 | +struct clk *icst_clk_setup(struct device *dev, |
| 336 | + const struct clk_icst_desc *desc, |
| 337 | + const char *name, |
| 338 | + const char *parent_name, |
| 339 | + struct regmap *map, |
| 340 | + enum icst_control_type ctype) |
353 | 341 | {
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354 | 342 | struct clk *clk;
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355 | 343 | struct clk_icst *icst;
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@@ -386,6 +374,7 @@ static struct clk *icst_clk_setup(struct device *dev,
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386 | 374 |
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387 | 375 | return clk;
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388 | 376 | }
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| 377 | +EXPORT_SYMBOL_GPL(icst_clk_setup); |
389 | 378 |
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390 | 379 | struct clk *icst_clk_register(struct device *dev,
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391 | 380 | const struct clk_icst_desc *desc,
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