@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
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struct reset_control * ahb_reset ;
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struct reset_control * por_reset ;
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struct reset_control * phy_reset ;
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+ struct reset_control * ext_reset ;
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struct regulator_bulk_data supplies [QCOM_PCIE_2_1_0_MAX_SUPPLY ];
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};
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@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
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if (IS_ERR (res -> por_reset ))
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return PTR_ERR (res -> por_reset );
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+ res -> ext_reset = devm_reset_control_get_optional_exclusive (dev , "ext" );
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+ if (IS_ERR (res -> ext_reset ))
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+ return PTR_ERR (res -> ext_reset );
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+
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res -> phy_reset = devm_reset_control_get_exclusive (dev , "phy" );
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return PTR_ERR_OR_ZERO (res -> phy_reset );
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}
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
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reset_control_assert (res -> axi_reset );
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reset_control_assert (res -> ahb_reset );
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reset_control_assert (res -> por_reset );
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+ reset_control_assert (res -> ext_reset );
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reset_control_assert (res -> phy_reset );
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clk_disable_unprepare (res -> iface_clk );
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clk_disable_unprepare (res -> core_clk );
@@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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goto err_deassert_ahb ;
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}
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+ ret = reset_control_deassert (res -> ext_reset );
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+ if (ret ) {
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+ dev_err (dev , "cannot deassert ext reset\n" );
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+ goto err_deassert_ahb ;
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+ }
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+
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/* enable PCIe clocks and resets */
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val = readl (pcie -> parf + PCIE20_PARF_PHY_CTRL );
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val &= ~BIT (0 );
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