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46 | 46 |
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47 | 47 | #define SAHARA_HDR_BASE 0x00800000
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48 | 48 | #define SAHARA_HDR_SKHA_ALG_AES 0
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49 |
| -#define SAHARA_HDR_SKHA_OP_ENC (1 << 2) |
50 |
| -#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3) |
51 |
| -#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3) |
| 49 | +#define SAHARA_HDR_SKHA_MODE_ECB 0 |
| 50 | +#define SAHARA_HDR_SKHA_OP_ENC BIT(2) |
| 51 | +#define SAHARA_HDR_SKHA_MODE_CBC BIT(3) |
52 | 52 | #define SAHARA_HDR_FORM_DATA (5 << 16)
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53 |
| -#define SAHARA_HDR_FORM_KEY (8 << 16) |
54 |
| -#define SAHARA_HDR_LLO (1 << 24) |
55 |
| -#define SAHARA_HDR_CHA_SKHA (1 << 28) |
56 |
| -#define SAHARA_HDR_CHA_MDHA (2 << 28) |
57 |
| -#define SAHARA_HDR_PARITY_BIT (1 << 31) |
| 53 | +#define SAHARA_HDR_FORM_KEY BIT(19) |
| 54 | +#define SAHARA_HDR_LLO BIT(24) |
| 55 | +#define SAHARA_HDR_CHA_SKHA BIT(28) |
| 56 | +#define SAHARA_HDR_CHA_MDHA BIT(29) |
| 57 | +#define SAHARA_HDR_PARITY_BIT BIT(31) |
58 | 58 |
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59 | 59 | #define SAHARA_HDR_MDHA_SET_MODE_MD_KEY 0x20880000
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60 | 60 | #define SAHARA_HDR_MDHA_SET_MODE_HASH 0x208D0000
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64 | 64 | #define SAHARA_HDR_MDHA_ALG_MD5 1
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65 | 65 | #define SAHARA_HDR_MDHA_ALG_SHA256 2
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66 | 66 | #define SAHARA_HDR_MDHA_ALG_SHA224 3
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67 |
| -#define SAHARA_HDR_MDHA_PDATA (1 << 2) |
68 |
| -#define SAHARA_HDR_MDHA_HMAC (1 << 3) |
69 |
| -#define SAHARA_HDR_MDHA_INIT (1 << 5) |
70 |
| -#define SAHARA_HDR_MDHA_IPAD (1 << 6) |
71 |
| -#define SAHARA_HDR_MDHA_OPAD (1 << 7) |
72 |
| -#define SAHARA_HDR_MDHA_SWAP (1 << 8) |
73 |
| -#define SAHARA_HDR_MDHA_MAC_FULL (1 << 9) |
74 |
| -#define SAHARA_HDR_MDHA_SSL (1 << 10) |
| 67 | +#define SAHARA_HDR_MDHA_PDATA BIT(2) |
| 68 | +#define SAHARA_HDR_MDHA_HMAC BIT(3) |
| 69 | +#define SAHARA_HDR_MDHA_INIT BIT(5) |
| 70 | +#define SAHARA_HDR_MDHA_IPAD BIT(6) |
| 71 | +#define SAHARA_HDR_MDHA_OPAD BIT(7) |
| 72 | +#define SAHARA_HDR_MDHA_SWAP BIT(8) |
| 73 | +#define SAHARA_HDR_MDHA_MAC_FULL BIT(9) |
| 74 | +#define SAHARA_HDR_MDHA_SSL BIT(10) |
75 | 75 |
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76 | 76 | /* SAHARA can only process one request at a time */
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77 | 77 | #define SAHARA_QUEUE_LENGTH 1
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81 | 81 | #define SAHARA_REG_CONTROL 0x08
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82 | 82 | #define SAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24)
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83 | 83 | #define SAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16)
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84 |
| -#define SAHARA_CONTROL_RNG_AUTORSD (1 << 7) |
85 |
| -#define SAHARA_CONTROL_ENABLE_INT (1 << 4) |
| 84 | +#define SAHARA_CONTROL_RNG_AUTORSD BIT(7) |
| 85 | +#define SAHARA_CONTROL_ENABLE_INT BIT(4) |
86 | 86 | #define SAHARA_REG_CMD 0x0C
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87 |
| -#define SAHARA_CMD_RESET (1 << 0) |
88 |
| -#define SAHARA_CMD_CLEAR_INT (1 << 8) |
89 |
| -#define SAHARA_CMD_CLEAR_ERR (1 << 9) |
90 |
| -#define SAHARA_CMD_SINGLE_STEP (1 << 10) |
91 |
| -#define SAHARA_CMD_MODE_BATCH (1 << 16) |
92 |
| -#define SAHARA_CMD_MODE_DEBUG (1 << 18) |
| 87 | +#define SAHARA_CMD_RESET BIT(0) |
| 88 | +#define SAHARA_CMD_CLEAR_INT BIT(8) |
| 89 | +#define SAHARA_CMD_CLEAR_ERR BIT(9) |
| 90 | +#define SAHARA_CMD_SINGLE_STEP BIT(10) |
| 91 | +#define SAHARA_CMD_MODE_BATCH BIT(16) |
| 92 | +#define SAHARA_CMD_MODE_DEBUG BIT(18) |
93 | 93 | #define SAHARA_REG_STATUS 0x10
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94 | 94 | #define SAHARA_STATUS_GET_STATE(x) ((x) & 0x7)
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95 | 95 | #define SAHARA_STATE_IDLE 0
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96 | 96 | #define SAHARA_STATE_BUSY 1
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97 | 97 | #define SAHARA_STATE_ERR 2
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98 | 98 | #define SAHARA_STATE_FAULT 3
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99 | 99 | #define SAHARA_STATE_COMPLETE 4
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100 |
| -#define SAHARA_STATE_COMP_FLAG (1 << 2) |
101 |
| -#define SAHARA_STATUS_DAR_FULL (1 << 3) |
102 |
| -#define SAHARA_STATUS_ERROR (1 << 4) |
103 |
| -#define SAHARA_STATUS_SECURE (1 << 5) |
104 |
| -#define SAHARA_STATUS_FAIL (1 << 6) |
105 |
| -#define SAHARA_STATUS_INIT (1 << 7) |
106 |
| -#define SAHARA_STATUS_RNG_RESEED (1 << 8) |
107 |
| -#define SAHARA_STATUS_ACTIVE_RNG (1 << 9) |
108 |
| -#define SAHARA_STATUS_ACTIVE_MDHA (1 << 10) |
109 |
| -#define SAHARA_STATUS_ACTIVE_SKHA (1 << 11) |
110 |
| -#define SAHARA_STATUS_MODE_BATCH (1 << 16) |
111 |
| -#define SAHARA_STATUS_MODE_DEDICATED (1 << 17) |
112 |
| -#define SAHARA_STATUS_MODE_DEBUG (1 << 18) |
| 100 | +#define SAHARA_STATE_COMP_FLAG BIT(2) |
| 101 | +#define SAHARA_STATUS_DAR_FULL BIT(3) |
| 102 | +#define SAHARA_STATUS_ERROR BIT(4) |
| 103 | +#define SAHARA_STATUS_SECURE BIT(5) |
| 104 | +#define SAHARA_STATUS_FAIL BIT(6) |
| 105 | +#define SAHARA_STATUS_INIT BIT(7) |
| 106 | +#define SAHARA_STATUS_RNG_RESEED BIT(8) |
| 107 | +#define SAHARA_STATUS_ACTIVE_RNG BIT(9) |
| 108 | +#define SAHARA_STATUS_ACTIVE_MDHA BIT(10) |
| 109 | +#define SAHARA_STATUS_ACTIVE_SKHA BIT(11) |
| 110 | +#define SAHARA_STATUS_MODE_BATCH BIT(16) |
| 111 | +#define SAHARA_STATUS_MODE_DEDICATED BIT(17) |
| 112 | +#define SAHARA_STATUS_MODE_DEBUG BIT(18) |
113 | 113 | #define SAHARA_STATUS_GET_ISTATE(x) (((x) >> 24) & 0xff)
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114 | 114 | #define SAHARA_REG_ERRSTATUS 0x14
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115 | 115 | #define SAHARA_ERRSTATUS_GET_SOURCE(x) ((x) & 0xf)
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116 | 116 | #define SAHARA_ERRSOURCE_CHA 14
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117 | 117 | #define SAHARA_ERRSOURCE_DMA 15
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118 |
| -#define SAHARA_ERRSTATUS_DMA_DIR (1 << 8) |
| 118 | +#define SAHARA_ERRSTATUS_DMA_DIR BIT(8) |
119 | 119 | #define SAHARA_ERRSTATUS_GET_DMASZ(x) (((x) >> 9) & 0x3)
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120 | 120 | #define SAHARA_ERRSTATUS_GET_DMASRC(x) (((x) >> 13) & 0x7)
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121 | 121 | #define SAHARA_ERRSTATUS_GET_CHASRC(x) (((x) >> 16) & 0xfff)
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