arm64/sysreg: Convert TRBIDR_EL1 register to automatic generation

This converts TRBIDR_EL1 register to automatic generation without
causing any functional change.

Cc: Will Deacon <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Suzuki K Poulose <[email protected]>
Cc: James Morse <[email protected]>
Cc: [email protected]
Cc: [email protected]
Reviewed-by: Mark Brown <[email protected]>
Signed-off-by: Anshuman Khandual <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Catalin Marinas <[email protected]>

Author: Anshuman Khandual

arch/arm64/include/asm/sysreg.h

@@ -227,14 +227,8 @@
 
 /*** End of Statistical Profiling Extension ***/
 
-#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
-
 #define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
 #define TRBSR_EL1_BSC_SHIFT		0
-#define TRBIDR_EL1_F			BIT(5)
-#define TRBIDR_EL1_P			BIT(4)
-#define TRBIDR_EL1_Align_MASK		GENMASK(3, 0)
-#define TRBIDR_EL1_Align_SHIFT		0
 
 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)

arch/arm64/tools/sysreg

@@ -2319,3 +2319,16 @@ Sysreg	TRBTRG_EL1	3	0	9	11	6
 Res0	63:32
 Field	31:0	TRG
 EndSysreg
+
+Sysreg	TRBIDR_EL1	3	0	9	11	7
+Res0	63:12
+Enum	11:8	EA
+	0b0000	NON_DESC
+	0b0001	IGNORE
+	0b0010	SERROR
+EndEnum
+Res0	7:6
+Field	5	F
+Field	4	P
+Field	3:0	Align
+EndSysreg