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AngeloGioacchino Del Regnobebarino
AngeloGioacchino Del Regno
authored and
bebarino
committed
clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
Various MSDC core clocks, used for multiple MSDC controller instances, share the same parent(s): in order to add parents selection in the mtk-sd driver to achieve an accurate clock rate for all modes, remove the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this will make sure that a clk_set_rate() call performed for a clock on a secondary controller will not change the rate of a common parent, which would result in an overclock or underclock of one of the controllers. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Markus Schneider-Pargmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Alexandre Mergnat <[email protected]> Reviewed-by: Alexandre Mergnat <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
1 parent 1775790 commit f235f6a

11 files changed

+93
-92
lines changed

‎drivers/clk/mediatek/clk-mt6765.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -406,15 +406,15 @@ static const struct mtk_mux top_muxes[] = {
406406
CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
407407
CLK_CFG_UPDATE, 11),
408408
/* CLK_CFG_3 */
409-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
409+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
410410
msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
411-
CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
412-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
411+
CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12, 0),
412+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
413413
msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
414-
CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
415-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
414+
CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13, 0),
415+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
416416
msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
417-
CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
417+
CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14, 0),
418418
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
419419
CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
420420
24, 2, 31, CLK_CFG_UPDATE, 15),

‎drivers/clk/mediatek/clk-mt6779.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -687,16 +687,16 @@ static const struct mtk_mux top_muxes[] = {
687687
0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
688688
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
689689
0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
690-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
691-
msdc50_hclk_parents, 0x70, 0x74, 0x78,
692-
16, 2, 23, 0x004, 22),
693-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
694-
msdc50_0_parents, 0x70, 0x74, 0x78,
695-
24, 3, 31, 0x004, 23),
690+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
691+
msdc50_hclk_parents, 0x70, 0x74, 0x78,
692+
16, 2, 23, 0x004, 22, 0),
693+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",
694+
msdc50_0_parents, 0x70, 0x74, 0x78,
695+
24, 3, 31, 0x004, 23, 0),
696696
/* CLK_CFG_6 */
697-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
698-
msdc30_1_parents, 0x80, 0x84, 0x88,
699-
0, 3, 7, 0x004, 24),
697+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel",
698+
msdc30_1_parents, 0x80, 0x84, 0x88,
699+
0, 3, 7, 0x004, 24, 0),
700700
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
701701
0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
702702
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",

‎drivers/clk/mediatek/clk-mt7981-topckgen.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -310,12 +310,12 @@ static const struct mtk_mux top_muxes[] = {
310310
pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
311311
0x1C0, 7),
312312
/* CLK_CFG_2 */
313-
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
314-
emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
315-
0x1C0, 8),
316-
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
317-
emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
318-
0x1C0, 9),
313+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
314+
emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
315+
0x1C0, 8, 0),
316+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
317+
emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
318+
0x1C0, 9, 0),
319319
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
320320
csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
321321
0x1C0, 10,

‎drivers/clk/mediatek/clk-mt7986-topckgen.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -193,12 +193,12 @@ static const struct mtk_mux top_muxes[] = {
193193
pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
194194
31, 0x1C0, 7),
195195
/* CLK_CFG_2 */
196-
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
197-
emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
198-
0x1C0, 8),
199-
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
200-
emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
201-
0x1C0, 9),
196+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
197+
emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
198+
0x1C0, 8, 0),
199+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
200+
emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
201+
0x1C0, 9, 0),
202202
MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
203203
f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
204204
0x1C0, 10),

‎drivers/clk/mediatek/clk-mt8173-topckgen.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -547,17 +547,17 @@ static const struct mtk_composite top_muxes[] = {
547547
MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
548548
/* CLK_CFG_3 */
549549
MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
550-
MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
551-
0x0070, 8, 3, 15),
552-
MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
553-
0x0070, 16, 4, 23),
554-
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
555-
0x0070, 24, 3, 31),
550+
MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
551+
0x0070, 8, 3, 15, 0),
552+
MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
553+
0x0070, 16, 4, 23, 0),
554+
MUX_GATE_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
555+
0x0070, 24, 3, 31, 0),
556556
/* CLK_CFG_4 */
557-
MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,
558-
0x0080, 0, 3, 7),
559-
MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
560-
0x0080, 8, 4, 15),
557+
MUX_GATE_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,
558+
0x0080, 0, 3, 7, 0),
559+
MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
560+
0x0080, 8, 4, 15, 0),
561561
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
562562
0x0080, 16, 2, 23),
563563
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
@@ -595,8 +595,8 @@ static const struct mtk_composite top_muxes[] = {
595595
MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents,
596596
0x00c0, 24, 3, 31),
597597
/* CLK_CFG_13 */
598-
MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
599-
0x00d0, 0, 3, 7),
598+
MUX_GATE_FLAGS(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
599+
0x00d0, 0, 3, 7, 0),
600600
MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
601601
MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents,
602602
0x00d0, 16, 2, 23),

‎drivers/clk/mediatek/clk-mt8183.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -487,14 +487,14 @@ static const struct mtk_mux top_muxes[] = {
487487
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
488488
spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15),
489489
/* CLK_CFG_4 */
490-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
491-
msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16),
492-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
493-
msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17),
494-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
495-
msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18),
496-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
497-
msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19),
490+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
491+
msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16, 0),
492+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
493+
msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17, 0),
494+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
495+
msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18, 0),
496+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
497+
msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19, 0),
498498
/* CLK_CFG_5 */
499499
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
500500
audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20),

‎drivers/clk/mediatek/clk-mt8186-topckgen.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -531,12 +531,12 @@ static const struct mtk_mux top_mtk_muxes[] = {
531531
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
532532
spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
533533
/* CLK_CFG_3 */
534-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
535-
msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12),
536-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
537-
msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13),
538-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
539-
msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14),
534+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
535+
msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12, 0),
536+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
537+
msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13, 0),
538+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
539+
msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14, 0),
540540
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio",
541541
audio_parents, 0x0070, 0x0074, 0x0078, 24, 2, 31, 0x0004, 15),
542542
/* CLK_CFG_4 */

‎drivers/clk/mediatek/clk-mt8188-topckgen.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1015,15 +1015,15 @@ static const struct mtk_mux top_mtk_muxes[] = {
10151015
uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
10161016
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
10171017
spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25),
1018-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
1019-
msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26),
1020-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
1021-
msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27),
1018+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
1019+
msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26, 0),
1020+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
1021+
msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27, 0),
10221022
/* CLK_CFG_7 */
1023-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
1024-
msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28),
1025-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
1026-
msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29),
1023+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
1024+
msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28, 0),
1025+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
1026+
msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29, 0),
10271027
MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
10281028
intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30),
10291029
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",

‎drivers/clk/mediatek/clk-mt8192.c

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -601,15 +601,16 @@ static const struct mtk_mux top_mtk_muxes[] = {
601601
uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
602602
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
603603
spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
604-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
605-
msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27),
604+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
605+
msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2,
606+
31, 0x004, 27, 0),
606607
/* CLK_CFG_7 */
607-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
608-
msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28),
609-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
610-
msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29),
611-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
612-
msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30),
608+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
609+
msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28, 0),
610+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
611+
msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29, 0),
612+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
613+
msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30, 0),
613614
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
614615
audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
615616
/* CLK_CFG_8 */

‎drivers/clk/mediatek/clk-mt8195-topckgen.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -930,15 +930,15 @@ static const struct mtk_mux top_mtk_muxes[] = {
930930
/* CLK_CFG_7 */
931931
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
932932
spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
933-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
934-
msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29),
935-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
936-
msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30),
937-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
938-
msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31),
933+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
934+
msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29, 0),
935+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
936+
msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30, 0),
937+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
938+
msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31, 0),
939939
/* CLK_CFG_8 */
940-
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
941-
msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0),
940+
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
941+
msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0, 0),
942942
MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
943943
intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
944944
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",

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