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Merge tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven: - Improved clock/reset handling for the R-Car USB2 Clock Selector - Conversion to json-schema of the Renesas CPG/MSSR DT bindings * tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema clk: renesas: rcar-usb2-clock-sel: Add reset_control clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
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Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Renesas Clock Pulse Generator / Module Standby and Software Reset
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maintainers:
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- Geert Uytterhoeven <[email protected]>
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description: |
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On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
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and MSSR (Module Standby and Software Reset) blocks are intimately connected,
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and share the same register block.
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They provide the following functionalities:
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- The CPG block generates various core clocks,
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- The MSSR block provides two functions:
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1. Module Standby, providing a Clock Domain to control the clock supply
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to individual SoC devices,
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2. Reset Control, to perform a software reset of individual SoC devices.
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properties:
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compatible:
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enum:
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- renesas,r7s9210-cpg-mssr # RZ/A2
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- renesas,r8a7743-cpg-mssr # RZ/G1M
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- renesas,r8a7744-cpg-mssr # RZ/G1N
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- renesas,r8a7745-cpg-mssr # RZ/G1E
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- renesas,r8a77470-cpg-mssr # RZ/G1C
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- renesas,r8a774a1-cpg-mssr # RZ/G2M
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- renesas,r8a774b1-cpg-mssr # RZ/G2N
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- renesas,r8a774c0-cpg-mssr # RZ/G2E
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- renesas,r8a7790-cpg-mssr # R-Car H2
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- renesas,r8a7791-cpg-mssr # R-Car M2-W
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- renesas,r8a7792-cpg-mssr # R-Car V2H
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- renesas,r8a7793-cpg-mssr # R-Car M2-N
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- renesas,r8a7794-cpg-mssr # R-Car E2
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- renesas,r8a7795-cpg-mssr # R-Car H3
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- renesas,r8a7796-cpg-mssr # R-Car M3-W
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- renesas,r8a77961-cpg-mssr # R-Car M3-W+
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- renesas,r8a77965-cpg-mssr # R-Car M3-N
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- renesas,r8a77970-cpg-mssr # R-Car V3M
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- renesas,r8a77980-cpg-mssr # R-Car V3H
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- renesas,r8a77990-cpg-mssr # R-Car E3
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- renesas,r8a77995-cpg-mssr # R-Car D3
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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items:
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enum:
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- extal # All
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- extalr # Most R-Car Gen3 and RZ/G2
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- usb_extal # Most R-Car Gen2 and RZ/G1
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'#clock-cells':
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/*-cpg-mssr.h>
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number, as defined in the datasheet.
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const: 2
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'#power-domain-cells':
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description:
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SoC devices that are part of the CPG/MSSR Clock Domain and can be
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power-managed through Module Standby should refer to the CPG device node
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in their "power-domains" property, as documented by the generic PM Domain
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bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
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const: 0
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'#reset-cells':
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description:
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The single reset specifier cell must be the module number, as defined in
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the datasheet.
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const: 1
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if:
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not:
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properties:
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compatible:
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items:
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enum:
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- renesas,r7s9210-cpg-mssr
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then:
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required:
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- '#reset-cells'
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0xe6150000 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};

Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt

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@@ -38,18 +38,29 @@ Required properties:
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- reg: offset and length of the USB 2.0 clock selector register block.
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- clocks: A list of phandles and specifier pairs.
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- clock-names: Name of the clocks.
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- The functional clock must be "ehci_ohci"
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- The functional clock of USB 2.0 host side must be "ehci_ohci"
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- The functional clock of HS-USB side must be "hs-usb-if"
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- The USB_EXTAL clock pin must be "usb_extal"
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- The USB_XTAL clock pin must be "usb_xtal"
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- #clock-cells: Must be 0
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- power-domains: A phandle and symbolic PM domain specifier.
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See power/renesas,rcar-sysc.yaml.
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- resets: A list of phandles and specifier pairs.
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- reset-names: Name of the resets.
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- The reset of USB 2.0 host side must be "ehci_ohci"
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- The reset of HS-USB side must be "hs-usb-if"
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Example (R-Car H3):
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usb2_clksel: clock-controller@e6590630 {
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compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
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"renesas,rcar-gen3-usb2-clock-sel";
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reg = <0 0xe6590630 0 0x02>;
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clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
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clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
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<&usb_extal>, <&usb_xtal>;
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clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
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#clock-cells = <0>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 703>, <&cpg 704>;
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reset-names = "ehci_ohci", "hs-usb-if";
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};

drivers/clk/renesas/Kconfig

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@@ -161,6 +161,7 @@ config CLK_RCAR_GEN3_CPG
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config CLK_RCAR_USB2_CLOCK_SEL
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bool "Renesas R-Car USB2 clock selector support"
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depends on ARCH_RENESAS || COMPILE_TEST
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select RESET_CONTROLLER
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help
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This is a driver for R-Car USB2 clock selector
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drivers/clk/renesas/rcar-usb2-clock-sel.c

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@@ -19,16 +19,24 @@
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#define USB20_CLKSET0 0x00
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#define CLKSET0_INTCLK_EN BIT(11)
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#define CLKSET0_PRIVATE BIT(0)
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#define CLKSET0_EXTAL_ONLY (CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)
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static const struct clk_bulk_data rcar_usb2_clocks[] = {
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{ .id = "ehci_ohci", },
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{ .id = "hs-usb-if", },
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};
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struct usb2_clock_sel_priv {
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void __iomem *base;
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struct clk_hw hw;
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struct clk_bulk_data clks[ARRAY_SIZE(rcar_usb2_clocks)];
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struct reset_control *rsts;
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bool extal;
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bool xtal;
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};
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static int usb2_clock_sel_enable(struct clk_hw *hw)
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{
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usb2_clock_sel_enable_extal_only(to_priv(hw));
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struct usb2_clock_sel_priv *priv = to_priv(hw);
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int ret;
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ret = reset_control_deassert(priv->rsts);
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if (ret)
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return ret;
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(priv->clks), priv->clks);
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if (ret) {
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reset_control_assert(priv->rsts);
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return ret;
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}
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usb2_clock_sel_enable_extal_only(priv);
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return 0;
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}
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static void usb2_clock_sel_disable(struct clk_hw *hw)
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{
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usb2_clock_sel_disable_extal_only(to_priv(hw));
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struct usb2_clock_sel_priv *priv = to_priv(hw);
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usb2_clock_sel_disable_extal_only(priv);
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clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clks), priv->clks);
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reset_control_assert(priv->rsts);
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}
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/*
@@ -119,6 +145,7 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
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struct usb2_clock_sel_priv *priv;
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struct clk *clk;
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struct clk_init_data init;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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memcpy(priv->clks, rcar_usb2_clocks, sizeof(priv->clks));
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ret = devm_clk_bulk_get(dev, ARRAY_SIZE(priv->clks), priv->clks);
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if (ret < 0)
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return ret;
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priv->rsts = devm_reset_control_array_get(dev, true, false);
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if (IS_ERR(priv->rsts))
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return PTR_ERR(priv->rsts);
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
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